• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.314-316
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• 2008

계통연계형 태양광 PCS는 주로 전압원 인버터와 전압의 승압을 위한 DC/DC컨버터, 즉 이단구조로 구성된다. Z-소스 인버터는 DC/DC컨버터 없이 전압을 승/감압할 수 있다. 3k급 계통연계형 태양광 PCS에 Z-소스 인버터를 적용하여 일단구조로 설계하였고 PSIM 시뮬레이션과 실험을 통하여 타당성을 검증하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 C
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• pp.2199-2201
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• 2005

High voltage power supply with pulse load($4.5{\mu}s$ and PRF 60Hz) condition is investigated which is of interest for applications like Klystron modulator power supplies with output voltage of 50kV. The performance specifications with this type of power supplies are very stringent demanding tight regulation(<0.01%) and high efficiency(> 85%). The solution to this problem as a single stage converter is very difficult. The final output voltage is obtained as sum of the output of SCPS & PCPS. The combination of the two stages can satisfy the pulse load specifications. The analysis of the voltage and power division between SCPS & PCPS has been done for the proposed topology. It has studied under various operating conditions of line and load. Simulation results are validated by experimental results.

• 전력전자학회논문지
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• 제25권5호
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• pp.358-368
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• 2020

Grid-connected inverters (GCIs) based on renewable energy sources play an important role in enhancing the sustainability of a society. Harmonic standards, such as IEEE 519 and P1547, which require the total harmonic distortion (THD) of the output current to be less than 5%, should be satisfied when GCIs are connected to a grid. However, achieving a current THD of less than 5% is difficult for GCIs with an output filter under a distorted grid condition. In this study, a novel harmonic compensation method that uses a digital lock-in amplifier (DLA) is proposed to eliminate harmonics effectively at the output of GCIs. Accurate information regarding harmonics can be obtained due to the outstanding performance of DLA, and such information is used to eliminate harmonics with a simple proportional-integral controller in a feedforward manner. The validity of the proposed method is verified through experiments with a 5 kW single-phase GCI connected to a real grid.

• Journal of Electrical Engineering and Technology
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• 제10권5호
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• pp.2018-2030
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• 2015

A two stage ac drive configuration consisting of a single-phase line commutated rectifier and a three-phase voltage source inverter (VSI) is very common in low and medium power applications. The deterministic pulse width modulation (PWM) methods like sinusoidal PWM (SPWM) could not be considered as an ideal choice for modern drives since they result mechanical vibration and acoustic noise, and limit the application scope. This is due to the incapability of the deterministic PWM strategies in sprawling the harmonic power. The random PWM (RPWM) approaches could solve this issue by creating continuous harmonic profile instead of discrete clusters of dominant harmonics. Insufficient filtering at dc link results in the amplitude distortion of the input dc voltage to the VSI and has the most significant impact on the spectral errors (difference between theoretical and practical spectra). It is obvious that the sprawling effect of RPWM undoubtedly influenced by input fluctuation and the discrete harmonic clusters may reappear. The influence of dc link fluctuation on harmonics and their spreading effect in the VSI remains invalidated. A case study is done with four different filter capacitor values in this paper and results are compared with the constant dc input operation. This paper also proposes an ingenious RPWM, a ripple dosed sinusoidal reference-random carrier PWM (RDSRRCPWM), which has the innate capacity of suppressing the effect of input fluctuation in the output than the other modern PWM methods. MATLAB based simulation study reveals the fundamental component, total harmonic distortion (THD) and harmonic spread factor (HSF) for various modulation indices. The non-ideal dc link is managed well with the developed RDSRRCPWM applied to the VSI and tested in a proto type VSI using the field programmable gate array (FPGA).

• 전자공학회논문지
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• 제51권9호
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• pp.82-90
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• 2014

본 논문에서는 선형성을 가진 파노라믹 스캔 라이다(PSL) 시스템용의 4-채널 차동 트랜스임피던스 증폭기 어레이를 0.18-um CMOS 공정을 이용하여 구현하였다. PSL시스템을 위한 성능의 비교분석을 위하여 전류모드 및 전압모드의 두 종류 트랜스임피던스 어레이 칩을 각각 구현하였으며, 채널당 1.25-Gb/s 동작속도를 갖도록 설계하였다. 먼저 전류모드 칩의 경우, 각 채널 광 수신입력단은 전류미러 구조로 구현하였으며, 특히 로컬 피드백 입력구조로 개선하여 낮은 입력저항과 낮은 잡음지수를 가질 수 있도록 설계하였다. 칩 측정 결과, 채널 당 $69-dB{\Omega}$ 트랜스임피던스 이득, 2.2-GHz 대역폭, 21.5-pA/sqrt(Hz) 평균 잡음 전류 스펙트럼 밀도, -20.5-dBm 수신감도, 및 1.8-V 전원전압에서 4채널 총 147.6-mW 소모전력을 보이며, 1.25-Gb/s 동작속도에서 크고 깨끗한 eye-diagram을 보인다. 한편, 전압모드 칩의 경우, 각 채널 광 수신입력단은 인버터 입력구조로 구현하여 낮은 잡음지수를 갖도록 설계하였다. 칩 측정 결과, 채널 당 $73-dB{\Omega}$ 트랜스임피던스 이득, 1.1-GHz 대역폭, 13.2-pA/sqrt(Hz) 평균 잡음 전류 스펙트럼 밀도, -22.8-dBm수신감도, 및 4채널 총 138.4-mW 소모전력을 보이며, 1.25-Gb/s 동작속도에서 크고 깨끗한 eye-diagra을 보인다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 B
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• pp.994-995
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• 2006

This paper presents a grid-connected photovoltaic (PV) system with direct coupled power quality control (PQC) algorithm, which uses an inner current control loop (PRT : polarized ramp time) and outer feedback control loop to improve grid power quality and maximum power point tracking (MPPT) of PV arrays. To reduce the complexity, cost and number of power conversions, which results in higher efficiency, single stage CCVSI (Current Controlled Voltage Source Inverter) is used. The proposed system operation has been divided into two modes (sunny and night). In night mode, the proposed system operates to compensate the reactive power demanded by nonlinear or variation in loads. in sunny mode, the proposed system performs PQC to reduce harmonic current and improve power factor as well as MPPT to supply active power from the PV arrays simultaneously. it is shown that the proposed system improves the system utilization factor to 100% which is generally low for PV system (20%). To verify the proposed system, a comprehensive evaluation with theoretical analysis and simulation results are presented.

• Journal of Power Electronics
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• 제15권4호
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• pp.1026-1034
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• 2015

In this paper, a unified control strategy using the current space vector modulation (CSVM) technique is proposed and applied to a bidirectional three-phase DC/AC converter. The operation of the converter changes with the direction of the power flow. In the charging mode, it works as a buck type rectifier; and during the discharging mode, it operates as a boost type inverter, which makes it suitable as an interface between high voltage AC grids and low voltage energy storage devices. This topology has the following advantages: high conversion efficiency, high power factor at the grid side, tight control of the charging current and fast transition between the charging and discharging modes. The operating principle of the mode analysis, the gate signal generation, the general control strategy and the transition from a constant current (CC) to a constant voltage (CV) in the charging mode are discussed. The proposed control strategy has been validated by simulations and experimental results obtained with a 1kW laboratory prototype using supercapacitors as an energy storage device.

• 전기전자학회논문지
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• 제23권1호
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• pp.151-158
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• 2019

본 논문에서는 태양광 및 풍력 발전소 등에 설치되어 있는 다수의 계통 연계형 인버터를 사용하여 Virtual D-STATCOM을 구성하고, 배전계통의 부하의 무효전력과 배전선로의 거리에 따른 케이블의 무효전력을 보상하여 기존의 단일 대용량 D-STATCOM을 설치하지 않고 변전소 인근의 PCC단의 무효전력을 보상하는 방법을 제시한다. 제안된 방식은 Matlab Simulink 시뮬레이션을 통해 동작원리와 무효전력 보상 성능을 검증하였다.

• 대한전자공학회논문지SD
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• 제49권8호
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• pp.22-26
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• 2012

본 논문에서는 0.18um CMOS(1P4M) 공정을 이용하여 HDMI용 액티브 광케이블에 적합한 채널당 2.5-Gb/s의 동작 속도를 갖는 광 수신기를 구현하였다. 광 수신기는 차동 증폭구조를 가지는 트랜스임피던스 증폭기, 5개의 증폭단을 갖는 리미팅 증폭기, 출력 버퍼단으로 구성된다. 트랜스임피던스 증폭기는 피드백 저항을 가진 인버터 입력구조로 구현함으로써 낮은 잡음지수와 작은 전력소모를 갖도록 설계하였다. 연이은 차동구조 증폭기 및 출력 버퍼단을 통해 전체 전압이득을 증가하였고, 리미팅 증폭단과의 연동을 용이하게 했다. 리미팅 증폭기는 다섯 단의 증폭단과 출력 버퍼단, 옵셋 제거 회로단으로 이루어져 있다. 시뮬레이션 결과, 제안한 광 수신기는 $91dB{\Omega}$ 트랜스임피던스 이득, 1.55 GHz 대역폭(입력단 0.32 pF의 포토다이오드 커패시턴스 포함), 16 pA/sqrt(Hz) 평균 잡음 전류 스펙트럼 밀도, 및 -21.6 dBm 민감도 ($10^{-12}$ BER)를 갖는다. 또한, DC 시뮬레이션 결과, 1.8-V의 전원전압에서 총 40 mW의 전력을 소모한다. 제작한 칩은 패드를 포함하여 $1.35{\times}2.46mm^2$의 면적을 갖는다. optical eye-diagram 측정 결과, 2.5-Gb/s 동작속도에서 크고 깨끗한 eye-diagram을 보인다.

• 방사선산업학회지
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• 제6권1호
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• pp.31-40
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• 2012

There are two methods to fabricate the readout electronic to a large-area CMOS image sensor (LACIS). One is to design and manufacture the sensor part and signal processing electronics in a single chip and the other is to integrate both parts with bump bonding or wire bonding after manufacturing both parts separately. The latter method has an advantage of the high yield because the optimized and specialized fabrication process can be chosen in designing and manufacturing each part. In this paper, LACIS chip, that is optimized design for the latter method of fabrication, is presented. The LACIS chip consists of a 3-TR pixel photodiode array, row driver (or called as a gate driver) circuit, and bonding pads to the external readout ICs. Among 4 types of the photodiode structure available in a standard CMOS process, $N_{photo}/P_{epi}$ type photodiode showed the highest quantum efficiency in the simulation study, though it requires one additional mask to control the doping concentration of $N_{photo}$ layer. The optimized channel widths and lengths of 3 pixel transistors are also determined by simulation. The select transistor is not significantly affected by channel length and width. But source follower transistor is strongly influenced by length and width. In row driver, to reduce signal time delay by high capacitance at output node, three stage inverter drivers are used. And channel width of the inverter driver increases gradually in each step. The sensor has very long metal wire that is about 170 mm. The repeater consisted of inverters is applied proper amount of pixel rows. It can help to reduce the long metal-line delay.