• Industrial Engineering and Management Systems
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• 제12권3호
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• pp.181-189
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• 2013

This paper proposes a two-phase genetic algorithm (GA) to solve the problem of obtaining an optimum configuration of a paired single row assembly line. We pair two single-row assembly lines due to the shared usage of several workstations, thus obtaining an optimum configuration by considering the material flow of the two rows simultaneously. The problem deals with assigning workstations to a sequence and selecting the best arrangement by looking at the length and width for each workstation. This can be considered as an enhancement of the single row facility layout problem (SRFLP), or the so-called paired SRFLP (PSRFLP). The objective of this PSRFLP is to find an optimal configuration that seeks to minimize the distance traveled by the material handler and even the use of the material handler itself if this is possible. Real-world applications of such a problem can be found for apparel, shoe, and other manual assembly lines. This research produces the schematic representation solution using the heuristic approach. The crossover and mutation will be utilized using the schematic representation solution to obtain the neighborhood solutions. The first phase of the GA result is recorded to get the best pair. Based on these best matched pairs, the second-phase GA can commence.

• Management Science and Financial Engineering
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• 제16권1호
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• pp.47-57
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• 2010

We present a new integer programming formulation and a class of valid inequalities for solving the one-dimensional facility layout problem, which leads to a very efficient solution method for the problem.

• 품질경영학회지
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• 제19권1호
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• pp.151-162
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• 1991

The purpose of this study is to propose a facility layout design algorithm based on artificial intelligence concept, and then to develop a computer program which is more practical than any other conventional facility layout design systems. The algorithm is composed of five step layout procedures; knowledge and data input, knowledge interpretation, priority determination, inference of layout design, and evaluation, In the step of priority determination, the algorithm is divided into single row and multi row layout problem. In the step of inference of layout design, alternatives are generated by constraints-directed reasoning and depth first search method based on artificial intelligence concept. Alternatives are evaluated by the moving cost and relationship value by interactive man-machine interface in the step of evaluation. As a case study, analytical considerations over conventional programs such as CRAFT and CORELAP was investigated and compared with algorithm propsed in this study. The proposed algorithm in this study will give useful practical tool for layout planner. The computer progran was written in C language for IBM PC-AT.

• 한국산학기술학회논문지
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• 제12권2호
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• pp.588-593
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• 2011

프로그레시브 노칭과 포밍금형에 있어서 박판성형해석에 의한 사전 분석은 제품을 양산하는데 꼭 거쳐야 하는 필수과정이다. 본 논문에서 연구한 Ez5는 일본 S 자동차의 미국 현지 공장에서 발주한 수출 금형을 가지고 스트립 레이아웃 설계에 관한 것을 연구한 것이다. 광폭 1열 1개 뽑기의 편측캐리어를 단 배열로 블랭크 레이아웃을 최적화하여 13개 공정으로 된 스트립 레이아웃설계를 완성하였다. 이런 형태의 금형수주는 앞으로 동시 다발적이고, 매우 빈번히 인터넷 공간상에서 발생할 것이며 금형에 대한 기술력을 갖춘 업체는 이러한 방식에 대응할 준비를 갖추어야 할 것이다.

• Wind and Structures
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• 제34권3호
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• pp.275-290
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• 2022

Mobile sand barriers are a new type sand-retaining structure that can be moved and arranged according to the engineering demands of sand control. When only used for sand trapping, mobile sand barriers could be arranged in single row. For the dual purposes of sand trapping and sand stabilization, four rows of mobile sand barriers can be arranged in a staggered form. To reveal the effect of plane layout, the included angle between sand barrier direction and wind direction on the characteristics of flow fields and the sand control laws of mobile sand barriers, numerical computations and wind tunnel tests were conducted. The results showed that inflows deflected after passing through staggered arrangement sand barriers due to changes in included angle, and the sand barrier combination exerted successive wind resistance and group blocking effects. An analysis of wind resistance efficiency revealed that the effective protection length of staggered arrangement sand barriers approximately ranged from the sand barrier to 10H on the leeward side (H is sand barrier height), and that the effective protection length of single row sand barriers roughly ranged from 1H on the windward side to 20H on the leeward side. The distribution of sand deposit indicated that the sand interception increased with increasing included angle in staggered arrangement. The wind-breaking and sand-trapping effects were optimal when included angle between sand barrier direction and wind direction is 60°-90°.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.249-250
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• 2008

In this paper, we propose the single polycrystalline silicon flash EEPROM IC with a new structure which does not need the high voltage switching circuit. The design of high voltage switching circuits which are needed for the data program and erase, has been an obstacle to develop the single-poly EEPROM. Therefore, we has proposed the new cell structure which uses the low voltage switching circuits and has designed the full chip. A new single-poly EEPROM cell is designed and the full chip including the control block, the analog block, row decoder block, and the datapath block is designed. And the each block is verified by using the computer simulation. In addition, the full chip layout is performed.

• Journal of Information Display
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• 제3권2호
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• pp.1-5
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• 2002

A CMOS driving circuit for active matrix type polymer electroluminescent displays was designed to develop an on-chip microdisplay on the single crystal silicon wafer substrate. The driving circuit is a conventional structure that is composed of the row, column and pixel driving parts. 256 gray scales were implemented using pulse amplitude modulation method. The 2-transistor driving scheme was adopted for the pixel driving part. The layout was carried out considering the compatibility with the standard CMOS process. Judging from the layout of the driving circuit, it turns that it is possible to implement a high-resolution display about 400 ppi resolution. Through the HSPICE simulation, it was verified that this circuit is capable of driving a VGA signal mode display and implementing 256 gray levels.

• 전자공학회논문지A
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• 제32A권4호
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• pp.93-102
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• 1995

This paper introduces a general purpose Associative Processor(AP) which is very efficient for search-oriented applications. The proposed architecture consists of three main functional blocks: Content-Addressable Memory(CAM) arry, row logic, and control section. The proposed AP is a Single-Instruction, Multiple-Data(SIMD) device based on a CAM core and an array of high speed processors. As an application for the proposed hardware, we present a parallel algorithm to solve a global routing problem in the layout process utilizing the processing capabilities of a rudimentary logic and the selective matching and writing capability of CAMs, along with basic algorithms such a minimum(maximum) search, less(greater) than search and parallel arithmetic. We have focused on the simultaneous minimization of the desity of the channels and the wire length by sedking a less crowded channel with shorter wire distance. We present an efficient mapping technique of the problem into the CAM structure. Experimental results on difficult examples, on randomly generated data, and on benchmark problems from MCNC are included.