• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1999.10a
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• pp.351-356
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• 1999

In this study, the characteristics of chip formation of the cold drawn Bi-S free machining steels were assessed. And for comparison, those of the cold drawn Pb-S free machining steel, the hot rolled low carbon steel which has MnS as free machining inclusions and the conventional steels were also investigated. During chip formation, the cold drawn free machining steels show relatively little change in thickness and width of chip compare to those of the conventional carbon steels. And a single parameter which indicates the degree of deformation during chip formation, 'chip cross-section area ratio' is introduced. The chip cross-section area. The variational patterns of cross-section area is divided by undeformed chip cross-section area. The variational patterns of the chip cross-section area ratio of the materials cut are similar to those of the shear strain values. The shear stress, however, seems to be dependent on the carbon content of the materials. The cold drawn BiS and Pb-S steels show nearly the same chip forming behaviors and the energy consumed during chip formation is almost same. A low carbon steel without free machining aids shows poor chip breakability due to its high ductility. By introducing a small amount of non-metallic inclusions such as MnS, Bi, Pb or merely increasing carbon content the chip breakability improves significantly.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.577-580
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• 2003

Stress state of chip formation zone is one of the main problems in metal cutting mechanics. In two-dimensional case this process is usually considered as consistent shears of work material along single of several shear surfaces. separating chip from workpiece. These shear planes are assumed to be trajectories of maximum shear stress forming corresponding slip-line field. This paper suggests new approach to the constriction of slip-line field, which Implies uniform compression in chip formation zone. On the base of given model it has been found that imaginary shear line in orthogonal cutting is close to the trajectory of maximum normal stress and the problem about its determination have been considered. It has been shown that there is a second central slip-line field inside chip, which corresponds well to experimental data about stress distribution on tool rake face and tool-chip contact length. The suggested model could be useful in solution of various problems of machining.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.61-71
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• 2007

The instruction level parallelism, which has been used to improve the performance of processors, expose its limit. The change of a control flow by a branch miss prediction is one of the obstacles that restrict the instruction level parallelism. The single chip multiprocessors have been developed to utilize the thread level parallelism. However, we could not use the maximum performance of the single chip multiprocessor in case of executing the coded programs without considering the multi-thread. In order to overcome the two performance degradation factors, in this paper, we suggest the concurrent branch execution method that applies to the multi-path execution method at a single chip multiprocessor. We executes all two flows of the conditional branch using the idle core processor. Through this, we can improve the processor's efficiency with blocking the control flow termination by the branch instruction and reducing the idle time. We analyze the effects of concurrent branch execution proposed in this paper through the simulation. As a result of that, concurrent branch execution reduces about 20% of idle time and improves the maximum 10% of the branch prediction accuracy. We show that our scheme improves the overall performance of maximum 39% compared to the normal single chip multiprocessor and maximum 27% compared to the superscalar processor.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.8
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• pp.3103-3120
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• 2015

This paper presents a single-phase energy metering chip with built-in calibration function to measure electric power quantities. The entire chip consists of an analog front end, a filter block, a computation engine, a calibration engine, and an external interface block. The key design issues are how to reduce the implementation costs of the computation engine from repeatedly used arithmetic operations and how to simplify calibration procedure and reduce calibration time. The proposed energy metering chip simplifies the computation engine using time-division multiplexed arithmetic units. It also provides a simple and fast calibration scheme by using integrated digital calibration functionality. The chip is fabricated with 0.18-μm six-layer metal CMOS process and housed in a 32-pin quad-flat no-leads (QFN) package. It operates at a clock speed of 4096 kHz and consumes 9.84 mW in 3.3 V supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.3-8
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• 2013

In CDMA-based systems, recently, researches on chip-level equalization have been studied in order to improve receiving performance when supporting high-rate data services. In this paper, we consider a chip-level LMMSE (linear minimum mean-squared error) receiver for D-TxAA (dual stream transmit antenna array) based single stream HSDPA MIMO systems using precoding weights. First, we will derive precoding weights for maximizing the total instantaneous received power. We will also analyze the effects of both transmit delay of precoding weights and mobile velocity on chip-level LMMSE receivers, which is verified through computer simulations in various mobile channel environments.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.63 no.2
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• pp.81-88
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• 2014

In this paper, an implementation of concurrent backoff delay process on a single chip with IEEE 802.15.4 hardware and 8051 processor core that can be used for analyzing the interference on IEEE 802.15.4 channels due to WiFi traffics is studied. The backoff delay process of IEEE 802.15.4 CSMA-CA algorithm is explained. The characteristics of random number generator, timer, and CCA register included in the single chip are described with their control procedure in order to implement the process. A concurrent backoff delay process to evaluate multiple IEEE 802.15.4 channels is proposed, and a method to service the associated tasks at sequentially ordered backoff delay events occurring on the channels is explained. For the implementation of the concurrent backoff delay process on a single chip IEEE 802.15.4 hardware, the elements for the single channel backoff delay process and their control procedure are used to be extended to multiple channels with little modification. The medium access delay on each channel, which is available after execution of the concurrent backoff delay process, is displayed on the LCD of an IEEE 802.15.4 channel analyzer. The experimental results show that we can easily identify the interference on IEEE 802.15.4 channels caused by WiFi traffics in comparison with the way displaying measured channel powers.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.471-474
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• 2001

Recently, due to demands of faster speed and extra features for the chip mounters, there has been ever-demanding needs for the basic technology. Until four or five years ago, chip mounters placing 0.3sec/chip were considered to be in the high speed category, but since then it has become a borderline for categorizing high speed machines capable of placing 0.1sec/chip. In this study, in order to analyze the vibration of head generated by the dynamic behavior of x-frame, FEM model is composed and modal analysis is performed to identify the dynamic characteristics of the structure. Those results are compared with the modal test in order to verify the model. In this paper, Several other factors, such as definition of dynamic accuracy, static accuracy and tolerance of the axis settling range, that might affect the dynamic behavior the head are discussed.

• ETRI Journal
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• v.26 no.6
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• pp.560-564
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• 2004

An analog front-end circuit for ISO/IEC 14443-compatible radio frequency identification (RFID) interrogators was designed and fabricated by using a $0.25{\mu}m$ double-poly CMOS process. The fabricated chip was operated using a 3.3 Volt single-voltage supply. The results of this work could be provided as reusable IPs in the form of hard or firm IPs for designing single-chip ISO/IEC 14443-compatible RFID interrogators.

• Proceedings of the IEEK Conference
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• 2001.06c
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• pp.85-86
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• 2001

3D parallel rasterizer on a single chip for high performance generates consistency problem. To solve this problem, 3D parallel rasterizer with consistency buffer Os proposed. This can simultaneously process a plurality of Primitives. Experimental results show 1.1-2.0x speedups using a simple model. This method can achieve high performance and cost effectiveness.

• Proceedings of the IEEK Conference
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• 2000.06d
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• pp.242-245
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• 2000

In this paper, we present a color interpolation technique based on artificial neural networks for a single-chip CCD (charge-coupled device) camera with a Bayer color filter array (CFA). Single-chip digital cameras use a color filter array and an interpolation method in order to regenerate high quality color images from sparsely sampled images. We applied 3-layer feedforward neural networks in order to interpolate missing pixel from surrounding pixels. And we compared the proposed method with conventional interpolation methods such as the proposed interpolation algorithm based on neural networks provides a better performance than the conventional interpolation algorithms.