• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.2
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• pp.80-86
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• 2011

This paper presents an integrated variable amplitude high voltage pulse generation circuit with low power and small size for driving industrial piezoelectric printer heads. To solve the problems of large size and power overhead of conventional pulse generators that usually assembled with multiple high-cost discrete ICs on a PCB board, we have designed a new integrated circuit (IC) chip. Since all the functions are integrated on to a single-chip it can achieve low cost and control the high-voltage output pulse with variable amplitudes as well. It can also digitally control the rising and falling times of an output high voltage pulse by using programmable RC time control of the output buffer. The proposed circuit has been designed and simulatedd in a 180[nm] Bipolar-CMOS-DMOS (BCD) technology using HSPICE and Cadence Virtuoso Tools. The proposed single-chip pulse generation circuit is suitable for use in industrial printer heads requiring a variable high voltage driving capability.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.10
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• pp.21-31
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• 1994

This paper describes the multichannel combined R2MFC/DTMF/CCT reciver which provides a signaling service functions for call processing control in digital switching system. Using the TMS320C25 DSP chip, we have implemented multi-function receriver shich processes 8 channels of R2MFC, DTMF, and CCT signals simultaneously. In order to increase the channel multiplicity of the combined receiver. R2MFC and CCT receiver were employed by discrete Fourier transform(DFT) method using Goertzel algorithm, and DTMFreceiver was employ by infinite impulse reponse(IIR) filtering method using 4KHz subsampling technique. The combined receiver has 4 function modes for each channel such as R2MFC, DTMF, CCT, and Idle modes. The function mode of each channel may be selected at any time by single-chip micro-controller(.mu.C). Hence, the number of channels assigned for each function mode can be adjusted dynamically according to the signaling traffic variations. From the experimental test results using the test-bed, it has been proved that the combined receiver statisfies all receiver satisfies all receiver specifications, and provides good channel multiplicity and performance, Therefore, it may give a great improvement than existing receiver in cost, reliability, availability, and serviceability.

• ETRI Journal
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• v.46 no.4
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• pp.708-715
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• 2024

We propose a 10-GHz 2 × 2 phased-array radio frequency (RF) receiver with an 8-bit linear phase and 15-dB gain control range using 65-nm complementary metal-oxide-semiconductor technology. An 8 × 8 phased-array receiver module is implemented using 16 2 × 2 RF phased-array integrated circuits. The receiver chip has four single-to-differential low-noise amplifier and gain-controlled phase-shifter (GCPS) channels, four channel combiners, and a 50-Ω driver. Using a novel complementary bias technique in a phase-shifting core circuit and an equivalent resistance-controlled resistor-inductor-capacitor load, the GCPS based on vector-sum structure increases the phase resolution with weighting-factor controllability, enabling the vector-sum phase-shifting circuit to require a low current and small area due to its small 1.2-V supply. The 2 × 2 phased-array RF receiver chip has a power gain of 21 dB per channel and a 5.7-dB maximum single-channel noise-figure gain. The chip shows 8-bit phase states with a 2.39° root mean-square (RMS) phase error and a 0.4-dB RMS gain error with a 15-dB gain control range for a 2.5° RMS phase error over the 10 to10.5-GHz band.

• The Korean Journal of Cytopathology
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• v.19 no.2
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• pp.119-125
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• 2008

This study was performed to compare the efficacy between a DNA chip method and a Hybrid-Capture II assay (HC-II) for detecting human papillomavirus in patients with intraepithelial lesions of the uterine cervix. From May, 2005, to June, 2006, 192 patients with abnormal colposcopic findings received cervical cytology, HC-II and HPV DNA chip tests, and colposcopic biopsy or conization. We compared the results of HC-II and HPV DNA chip in conjunction with liquid based cervical cytology (LBCC) and confirmed the results of biopsy or conization. The sensitivity of the HPV DNA chip test was higher than HC-II or LBCC. The HPV DNA chip in conjunction with LBCC showed higher sensitivity than any single method and higher sensitivity than HC-II with LBCC. We confirmed that the HPV DNA chip test was more sensitive for detecting HPV in cervical lesions than HC-II, and that it would provide more useful clinical information about HPV type and its multiple infections.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.8
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• pp.35-43
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• 1992

We have presented the tracing algorithm for center pixel of character image. Character image was read by scanner device. Performing the tracing process, it can be possible to detect feature points, such as branch point, stroke of 4 directions. So, the tracing process covers the thinning and feature point detection process for improving the processing time. Usage of suggested tracing algorithm instead of thinning that is the preprocessing of character recognition increases speed up to 5 times. The preprocessing chip has been designed by using single layer perceptron algorithm.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.763-766
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• 1998

This paper describes the microarchitecture of the integer processor unit of RAPTOR which is an on-chip multiprocessor. The integer processor unit implements the 64-bit SPARC-V9 architecture and supports by hardware out-of-order instruction execution. The unit is designed to be handy so that multiple copies of the unit cn be integrated with cache memories into a single chip. The design was proceeded in a top-down manner. The hardware description and its verfication were performed using Verilog-HDL.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.751-754
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• 1998

This research aims at developing a single chip multiprocessor for high-performance computer system. Our design approach is to design a relatively small and simple processor unit and to integrate multiple copies of the unit in an efficient way. The proposed multiprocessor is composed of four CPUs and one graphic coprocessor. The four CPUs share the graphic coprocessor and each CPU implements the 64-bit SPARC-V9 instruction set architecture. This paper gives an overview of the proposed microarchitecture and discusses the considerations made in the course of the design.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.2
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• pp.49-52
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• 2001

This paper presents product level considerations for multichip packaging as a cost effective alternative to single chip packaging in the design and manufacture of mobile telephony products. Important aspects include component functionality and complexity, acquisition and logistics costs, product modularity and integration. Multichip packaging offers unique solutions and significant system level cost savings in many applications including RF modules, digital matrix functions and product options such as security, data storage, voice recognition, etc.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.782-785
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• 2002

Power amplifier of wireless communication tranceiver can be effectually controlled output power. And small size and low power dissipation are indispensable to portable system. In this paper, to reduce the size of portable tranceiver, inductor is integrated in a single chip. And to reduce power dissipation, a power amplifier that can be digitally controlled output power, is proposed and designed.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.399-402
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• 2000

The reduction of chip area and delay is important purpose of Scheduling in High-Level Synthesis. This paper presents a scheduling approach with component selection. After obtaining a initial schedule taking only single-functional u-nits, the component selection of our approach attempts the reduction of chip area and/or delay by the selection more suitable components in a component library using Simulated Annealing.