• Journal of Gastric Cancer
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• v.18 no.1
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• pp.37-47
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• 2018

Purpose: The endoscopic management of a fully covered self-expandable metal stent (SEMS) has been suggested for the primary treatment of patients with anastomotic leaks after total gastrectomy. Embedded stents due to tissue ingrowth and migration are the main obstacles in endoscopic stent management. Materials and Methods: The effectiveness and safety of endoscopic management were evaluated for anastomotic leaks when using a benign fully covered SEMS with an anchoring thread and thick silicone covering the membrane to prevent stent embedding and migration. We retrospectively reviewed the data of 14 consecutive patients with gastric cancer and anastomotic leaks after total gastrectomy treated from January 2009 to December 2016. Results: The technical success rate of endoscopic stent replacement was 100%, and the rate of complete leaks closure was 85.7% (n=12). The mean size of leaks was 13.1 mm (range, 3-30 mm). The time interval from operation to stent replacement was 10.7 days (range, 3-35 days) and the interval from stent replacement to extraction was 32.3 days (range, 18-49 days). The complication rate was 14.1%, and included a single jejunal ulcer and delayed stricture at the site of leakage. No embedded stent or migration occurred. Two patients died due to progression of pneumonia and septic shock 2 weeks after stent replacement. Conclusions: A benign fully covered SEMS with an anchoring thread and thick membrane is an effective and safe stent in patients with anastomotic leaks after total gastrectomy. The novelty of this stent is that it provides complete prevention of stent migration and embedding, compared with conventional fully covered SEMS.

• Structural Engineering and Mechanics
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• v.86 no.2
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• pp.261-276
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• 2023

The use of the ordinary double nut (i.e., ODN) composed of a master nut (i.e., M-nut) and a slave nut (i.e., S-nut) is a highly efficient method to prevent bolts loosening. A novel double nut (i.e., FODN) composed of a master nut (i.e., M-nut) and flat slave nut (i.e., FS-nut) is proposed to save raw materials. The bolt fastening tests with single nut, ODN and FODN are performed to investigate the preload and counterbalance forces. Corresponding finite element analysis (FEA) models are established and validated by comparing the preload with the experimental results. The load-bearing capacity, the extrusion effect, and the contact stress of each engaged thread for ODN and FODN are observed by FEA. The experimental and simulated results revealed that the bolt fastening with double-nut has different load-transferring mechanisms from single-nut. Nevertheless, for double-nut/bolt assemblies, the FS-nut can provide load transfer that is like that of the S-nut, and the FODN is a reasonable and reliable fastening method. Furthermore, based on the theory of Yamamoto, a formula considering the extrusion effect is proposed to calculate the preload distribution of the double-nut, which is applicable to varying thicknesses of slave-nuts in double-nut/bolt assemblies.

• ETRI Journal
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• v.42 no.4
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• pp.468-479
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• 2020

The proposed AI processor architecture has high throughput for accelerating the neural network and reduces the external memory bandwidth required for processing the neural network. For achieving high throughput, the proposed super thread core (STC) includes 128 × 128 nano cores operating at the clock frequency of 1.2 GHz. The function-safe architecture is proposed for a fault-tolerance system such as an electronics system for autonomous cars. The general-purpose processor (GPP) core is integrated with STC for controlling the STC and processing the AI algorithm. It has a self-recovering cache and dynamic lockstep function. The function-safe design has proved the fault performance has ASIL D of ISO26262 standard fault tolerance levels. Therefore, the entire AI processor is fabricated via the 28-nm CMOS process as a prototype chip. Its peak computing performance is 40 TFLOPS at 1.2 GHz with the supply voltage of 1.1 V. The measured energy efficiency is 1.3 TOPS/W. A GPP for control with a function-safe design can have ISO26262 ASIL-D with the single-point fault-tolerance rate of 99.64%.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.5
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• pp.817-828
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• 2017

It is very hard to find the system which processes single 10Gbps stream, and the related application is also rare. But in the field of science such as physics and astronomy, these high speed systems have been widely used and now more upgraded performance is expected. For this reason, high speed network based storage which captures and records 10Gbps level of packets was developed for the support of small astronomical company in KASI. But for the use of the system in research, system performance should be not only evaluated but also optimized. In this paper, we first implement system environment for the performance evaluation and discuss the experiment procedure and solution to acquire numerical results.

• Journal of The Korean Astronomical Society
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• v.49 no.4
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• pp.157-162
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• 2016

High resolution reconstruction technology is developed to help enhance the spatial resolution of observational images for ground-based solar telescopes, such as speckle masking. Near real-time reconstruction performance is achieved on a high performance cluster using the Message Passing Interface (MPI). However, much time is spent in reconstructing solar subimages in such a speckle reconstruction. We design and implement a novel parallel method for speckle masking reconstruction of solar subimage on a shared memory machine using the OpenMP. Real tests are performed to verify the correctness of our codes. We present the details of several parallel reconstruction steps. The parallel implementation between various modules shows a great speed increase as compared to single thread serial implementation, and a speedup of about 2.5 is achieved in one subimage reconstruction. The timing result for reconstructing one subimage with 256×256 pixels shows a clear advantage with greater number of threads. This novel parallel method can be valuable in real-time reconstruction of solar images, especially after porting to a high performance cluster.

• Journal of IKEEE
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• v.20 no.1
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• pp.75-81
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• 2016

This paper proposes a design of the tile based on graphic pipeline to improve the graphic application performance in SIMT based GP-GPU. The proposed Tile based on graphics pipeline avoids unnecessary graphic processing operation, and processes the rasterization step in parallel. The massive data processing in parallel through SIMT architecture improve the computational performance, thereby improving the 3D graphic pipeline performance. The more vertex data of 3D model, the higher performance. The proposed structure was confirmed to improve processing performance of up to 3 times from about 1.18 times as compared to 'RAMP' and previous studies.

• Design & Manufacturing
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• v.11 no.2
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• pp.25-28
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• 2017

Semiconductor equipment manufacturers desire to enhance efficiency of Sub Fab to increase semiconductor productivity. For this reason, Sub Fab equipment manufacturers are developing Integrated System that combined modules with multiple facilities. Integrated System is required to apply Mount Leveler of Wedge Type in compliance with weight increase compared with existing single equipment and product shape change. This thesis analyzes main design variables of components of Wedge Mount Leveler and carries out structure analysis using ANSYS, finite element analysis program Analysis shows that main design variables of components of Wedge Mount Leveler has self-locking condition by friction force of Wedge and adjusting bolt. Each friction force hinges upon Wedge angle and Friction Coefficient of contact surface and upon the thread angle and Friction Coefficient of contact surface. Also, as a result of carrying out structure analysis of Wedge Mount Leveler, deflection and stress appears in different depending on the height of the level.

• Journal of KIISE:Computing Practices and Letters
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• v.5 no.6
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• pp.793-800
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• 1999

TMN Agent Platform은 망 요소의 운영상태와 자원들을 GDMO에 따라 관리객체(Managed Object : MO)로 모델링 하고, 자원들의 현재 상태를 유지하며, 관리자(Manager)로부터의 망 관리 기능 요구에 따라 조작된다. 그러므로, 에이전트의 성능향상은 전체적인 통신망 관리의 성능향상에 직접적인 영향을 미친다.본 논문에서는 TMN 에이전트의 기능요구 사항을 분석하고, 이를 토대로 성능향상을 위해 멀티스레드 기법을 사용하는 병렬 처리 구조의 TMN Agent Platform의 기능구조를 제시한다. 또한 에이전트와 다양한 자원들간의 효율적인 메시지전달을 위한 체계를 제시하며, 구현된 TMN Agent Platform의 성능을 분석한다.Abstract TMN Agent manages the operational status and real-resources of network elements, such as switching nodes and transmission systems. It performs the requested management functions from manager and maintains consistent status data of real-resource. The performance of agent system affects directly the performance of network management operation. If the agent is implemented by sequential processing scheme with single process, the agent processing can be delayed or blocked according to the status of real-resources. This problem can be solved by parallel and distributed processing scheme.To improve the processing performance of TMN Agent, we propose a TMN Agent Platform's functional architecture that is based on parallel processing with multi-tread and effective message transferring scheme between agent and various real-resource. We analyze the performance of the implemented TMN Agent Platform.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.2
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• pp.89-97
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• 2009

Embedded systems widely used in ubiquitous environments usually employ an event-driven programming model instead of thread-based programming model in order to create a more robust system that uses less memory. However, as the software for embedded systems becomes more complex, it becomes hard to program as a single event handler using the event-driven programming model. This paper discusses the implementation of non-preemptive real-time scheduling theory for the design of embedded systems. To this end, we present an efficient schedulability test method for a given non-preemptive task set using a sufficient condition. This paper also shows that the notion of sub-tasks in embedded systems can overcome the problem of low utilization that is a main drawback of non-preemptive scheduling.

• Journal of Information Processing Systems
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• v.15 no.1
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• pp.151-158
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• 2019

With the recent advances of memory technologies, high-performance non-volatile memories such as non-volatile dual in-line memory module (NVDIMM) have begun to be used as an addition or an alternative to server-side storages. When these memory bus-connected storages (MBSs) are installed over non-uniform memory access (NUMA) servers, the distance between NUMA nodes and MBSs is one of the crucial factors that influence file processing performance, because the access latency of a NUMA system varies depending on its distance from the NUMA nodes. This paper presents the design and implementation of a high-performance logical volume manager for MBSs, called MBS-LVM, when multiple MBSs are scattered over a NUMA server. The MBS-LVM consolidates the address space of each MBS into a single global address space and dynamically utilizes storage spaces such that each thread can access an MBS with the lowest latency possible. We implemented the MBS-LVM in the Linux kernel and evaluated its performance by porting it over the tmpfs, a memory-based file system widely used in Linux. The results of the benchmarking show that the write performance of the tmpfs using MBS-LVM has been improved by up to twenty times against the original tmpfs over a NUMA server with four nodes.