• 전자공학회논문지A
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• 제33A권4호
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• pp.152-161
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• 1996

In tis work, a three-stage pipelined A/D converter (ADC) was implemented to obtain 10-bit resolution at a conversion rate of 20 msamples/s for video applications. The ADC consists of three identical stages employing a mid-rise coding technique. The interstage errors such as offsets and clock feedthrough are digitally corrected in digitral logic by one overlapped bit between stages. The proposed ADC is optimized by adopting a unit-capacitor array architecture in the MDAC to improve the differential nonlinearity and the yield. Reduced power dissipation has been achieve dby using low-power latched comparators. The prototype was fabricated in a 0.8$\mu$m p-well CMOS technology. The ADC dissipates 160 mW at a 20 MHz clock rate with a 5 V single supply voltage and occupies a die area of 7 mm$^{2}$(2.7 mm $\times$ 2.6mm) including bonding pads and stand-alone internal bias circuit. The typical differential and integral nonlinarities of the prototype are less than $\pm$ 0.6 LSB and $\pm$ 1 LSB, respectively.

• Journal of Power Electronics
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• 제11권3호
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• pp.264-270
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• 2011

In this paper a novel passive snubber is proposed, which can suppress the voltage spike across the bridge leg of the isolated full-bridge boost topology. The snubber is composed of capacitors, inductors and diodes. Two capacitors connected in series are used to absorb the voltage spike and the energy of each capacitor can be transferred to the load during one switching cycle by the resonance of the inductors and capacitors. The operational principle of the passive snubber is analyzed in detail based on a three-phase power factor correction (PFC) converter, and the design considerations of both the converter and the snubber are given. Finally, a 3kW laboratory-made prototype is built. The experimental results verify the theoretical analysis and evaluations. They also prove the validity and feasibility of the proposed methods.

• 한국자동차공학회논문집
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• 제21권5호
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• pp.15-24
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• 2013

Numerical studies were conducted to investigate the internal flow field and combustion characteristics of DISI engine with methanol blended in gasoline. Dual injection was applied and the characteristics were compared to single injection strategy. The amount of the fuel injection was corresponded to air-fuel ratio of each fuel for complete combustion. The preforming model in this study, software STAR-CD was employed for both modeling and solving. The operating speed condition were at 4000 rpm/WOT (Wide open throttle) where the engine was fully warmed. The results of single injection with M28 showed that the uniformity, equivalence ratio, in-cylinder pressure and temperature increased comparing to gasoline (M0). When dual injection was applied, there was no significant change in uniformity and equivalence ratio but the in-cylinder pressure and temperature increased. When M28 fuel and single injection was applied, the CO (Carbon monoxide) and NO (Nitrogen oxides) emission inside the combustion chamber increased approximately 36%, 9% comparing with benchmarking case in cylinder prior to TWC (Three Way Catalytic converter). When dual stage injection was applied, both CO and NO emission amount increased.

• 한국정보전자통신기술학회논문지
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• 제9권4호
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• pp.419-427
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• 2016

본 논문에서는 저면적 64bit MTP IP를 설계하였다. 저면적 설계기술로는 MTP cell의 inhibit voltage를 기존의 VPP/3과 VNN/3 전압 대신 모두 0V를 사용하므로 VPPL(=VPP/3) regulator 회로와 VNNL(VNN/3) charge pump 회로를 제거하였다. 그리고 external pad를 이용하여 VPP program voltage를 forcing하므로 VPP charge pump 회로를 제거하였다. 또한 VNN charge pump는 VPP 전압을 이용하여 1-stage negative charge pump 회로로 pumping해서 -VPP의 전압을 공급하도록 설계를 하였다. 설계된 64bit MTP IP size는 $377.585{\mu}m{\times}328.265{\mu}m$(=0.124mm2)이며, DC-DC converter관련 layout size는 기존의 회로 대비 76.4%를 줄였다.

• Journal of Electrical Engineering and Technology
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• 제3권3호
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• pp.391-400
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• 2008

Multi-pulse topology of converters using elementary six-pulse GTO - VSC (gate turn off based voltage source converter) operated under fundamental frequency switching (FFS) control is widely adopted in high power rating static synchronous compensators (STATCOM). Practically, a 48-pulse ($6{\times}8$ pulse) configuration is used with the phase angle control algorithm employing proportional and integral (PI) control methodology. These kinds of controllers, for example the ${\pm}80MVAR$ compensator at Inuyama switching station, KEPCO, Japan, employs two stages of magnetics viz. intermediate transformers (as many as VSCs) and a main coupling transformer to minimize harmonics distortion in the line and to achieve a desired operational efficiency. The magnetic circuit needs altogether nine transformers of which eight are phase shifting transformers (PST) used in the intermediate stage, each rating equal to or more than one eighth of the compensator rating, and the other one is the main coupling transformer having a power rating equal to that of the compensator. In this paper, a two-level 48-pulse ${\pm}100MVAR$ STATCOM is proposed where eight, six-pulse GTO-VSC are employed and magnetics is simplified to single-stage using four transformers of which three are PSTs and the other is a normal transformer. Thus, it reduces the magnetics to half of the value needed in the commercially available compensator. By adopting the simple PI-controllers, the model is simulated in a MATLAB environment by SimPowerSystems toolbox for voltage regulation in the transmission system. The simulation results show that the THD levels in line voltage and current are well below the limiting values specified in the IEEE Std 519-1992 for harmonic control in electrical power systems. The controller performance is observed reasonably well during capacitive and inductive modes of operation.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2006년도 춘계학술대회 논문집
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• pp.387-390
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• 2006

This paper presents a novel soft-switching PWM utility frequency AC to high frequency AC power conversion circuit Incorporating boost-half-bridge inverter topology, which is more suitable and acceptable for cost effective consumer induction heating applications. The operating principle and the operation modes are presented using the switching mode and the operating voltage and current waveforms. The performances of this high-frequency inverter using the latest IGBTs are illustrated, which includes high frequency power regulation and actual efficiency characteristics based on zero voltage soft switching (ZVS) operation ranges and the power dissipation as compared with those of the previously developed high-frequency inverter. In addition, a dual mode control scheme of this high frequency inverter based on asymmetrical pulse width modulation (PWM) and pulse density modulation (PDM) control scheme is discussed in this paper in order to extend the soft switching operation ranges and to improve the power conversion efficiency at the low power settings. The power converter practical effectiveness is substantially proved based on experimental results from practical design example.

• 정보처리학회논문지A
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• 제11A권2호
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• pp.195-202
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• 2004

본 연구에서 매우 정밀한 샘플링을 필요로 하는 고해상도 비디오 응용면을 위하여 병렬 파이프라인 아날로그 디지털 변환기(ADC)를 설계하였다. 본 ADC의 구조는 4 채널의 10-비트 파이프라인 ADC를 병력 time-interleave로 구성한 구조로서 이 구조에서 채널 당 샘플링 속도의 4배인 200MS/s의 샘플링 속도를 얻을 수 있었다. 변환기에서 핵심이 되는 구성요소는 Sample and Hold 증폭기(SHA), 비교기와 연산증폭기이며 먼저 SHA를 전단에 설치하여 시스템 타이밍 요구를 완화시키고 고속변환과 고속 입력신호의 처리론 가능하게 하였다. ADC 내부 단들의 1-비트 DAC, 비교기 및 2-이득 증폭기는 한 개의 switched 캐패시터 회로로 통합하여 고속동작은 물론 저 전력소비가 가능한 특성을 갖도록 하였다. 본 연구의 연산증폭기는 2단 차동구조에 부저항소자를 사용하여 높은 DC 이득을 갖도록 보강하였다. 본 설계에서 각 단에 D-플립플롭(D-FF)을 사용한 지연회로를 구성하여 변환시 각 비트신호를 정렬시켜 타이밍 오차를 최소화하였다. 된 변환기는 3.3V 공급전압에서 280㎽의 전력소비를 갖고 DNL과 INL은 각각 +0.7/-0.6LSB, +0.9/-0.3LSB이다.

• 대한전자공학회논문지SD
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• 제48권10호
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• pp.72-81
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• 2011

본 논문에서는 IEEE754 표준의 단정도 및 배정도를 지원하는 새로운 부동소수점 변환기를 제안하고 설계하였다. 제안된 변환기는 부호 있는 정수(32비트/64비트)와 부동소수점(단정도/배정도) 간 변환, 부호 없는 정수(32비트/64비트)를 부동소수점(단정도/배정도)으로의 변환, 부동소수점 단정도와 배정도 간 변환뿐만 아니라 부호 있는 고정소수점(32비트 64비트)과 부동소수점(단정도 배정도) 간 변환을 지원한다. 모든 입력 형태를 하나의 형태로 만드는 새로운 내부 형태를 정의함으로써 출력 형태의 표현 범위에 따른 오버플로우 검사를 쉽게 하도록 하였다. 내부 형태는 IEEE754 2008 표준에서 정의된 부동소수점 배정도의 확장된 형태(extended format)와 유사하다. 이 표준에서는 부동소수점 배정도의 확장된 형태(extended format)의 최소 지수부 비트폭은 15비트라고 명시하지만 제안된 컨버터를 구현하는데 11비트만으로도 충분하다. 또한 덧셈기가 대신 +1 증가기를 사용하면서 라운딩 연산과 음수의 정확한 표현이 가능하도록 변환기의 라운딩 스테이지를 최적화하였다. 단일 클럭 사이클 데이터패스와 5단 파이프라인 데이터패스를 설계하였다. 변환기의 두 데이터패스에 대한 HDL 모델을 기술한 후에 Synopsys design compiler를 사용하여 TSMC 180nm 공정 라이브러리로 합성하였다. 합성 결과의 셀 면적은 12,886 게이트(2입력 NAND 게이트 기준)이고 최대 동작 주파수는 411MHz이다.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• 제3B권3호
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• pp.147-154
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• 2003

This paper presents a high-frequency boost type ZVS-PWM chopper-fed DC-DC power converter with a single active auxiliary edge-resonant snubber at the load stage which can be designed for power conditioners such as solar photovoltaic generation, fuel cell generation, battery and super capacitor energy storages. Its principle operation in steady-state is described in addition to a prototype setup. The experimental results of boost type ZVS-PWM chopper proposed here, are evaluated and verified with a practical design model in terms of its switching voltage and current waveforms, the switching v-i trajectory and the temperature performance of IGBT module, the actual power conversion efficiency, and the EMI of radiated and conducted emissions, and then discussed and compared with the hard switching scheme from an experimental point of view. Finally, this paper proposes a practical method to suppress parasitic oscillation due to the active auxiliary resonant switch at ZCS turn-off mode transition with the aid of an additional lossless clamping diode loop, and can be reduced the EMI conducted emission.

• Journal of Power Electronics
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• 제18권4호
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• pp.1015-1026
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• 2018

A family of dual-DC-input (DI) dual-buck inverters (DBIs) is proposed by employing a DI switching cell as the input of traditional DBIs. Three power ports, i.e. a low voltage DC input port, a high voltage DC input port and an AC output port, are provided by the proposed DI-DBIs. A low voltage DC source, whose voltage is lower than the peak amplitude of the AC side voltage, can be directly connected to the DI-DBI. This supplies power to the AC side in single-stage power conversion. When compared with traditional DBI-based two-stage DC/AC power systems, the conversion stages are reduced, and the power rating and power losses of the front-end Boost converter of the DI-DBI are reduced. In addition, five voltage-levels are generated with the help of the two DC input ports, which is a benefit in terms of reducing the voltage stresses and switching losses of switches. The topology derivation method, operation principles, modulation strategy and characteristics of the proposed inverter are analyzed in-depth. Experimental results are provided to verify the effectiveness and feasibility of the proposed DI-DBIs.