• 제목/요약/키워드: Single phase phase-locked loop

검색결과 81건 처리시간 0.022초

단상 계통연계 운전을 위한 다양한 PLL 기법의 성능 평가 (Performance Evaluation of Various PLL Techniques for Single Phase Grids)

  • 파르타 사라티 다스;김경화
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2013년도 전력전자학술대회 논문집
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    • pp.47-48
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    • 2013
  • In order to evaluate the response of the grid-connected systems, Phase lock technology is widely used in power electronic devices to obtain the phase angle, amplitude, and frequency of the grid voltage because phase locked loop (PLL) algorithms are very important for grid synchronization and monitoring in the grid connected power electronic devices. This paper presents a performance evaluation in tracking grid angular frequency through single phase synchronization techniques which are an enhanced PLL (EPLL), second-order generalized integrator-PLL (SOGI-PLL), and second-order generalized integrator-frequency locked loop (SOGI-FLL). These techniques are properly analyzed through several steps to get the best technique which can track the frequency accurately and smoothly.

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Adaptive Linear Combiner로 구성된 Phase Locked Loop 시스템의 특성분석 (Performance Analysis of Phase-Locked Loop system composed of Adaptive Linear Combiner)

  • 배병열;한병문
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2005년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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    • pp.143-145
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    • 2005
  • A typical method to control the single-phase power converter system is to utilize the zero-crossing PLL. However, this method is vulnerable to the voltage disturbance and affects the performance of controller. This paper proposes a new single-phase PLL system that is composed of the adaptive linear combiner and the PI control. The operational principle was analyzed through theoretical approach and the performance was verified through simulations with MATLAB. The proposed PLL system shows rapidness and robustness in control under the voltage disturbances such as the sag, harmonics, and phase jump.

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Effects of Input Harmonics, DC Offset and Step Changes of the Fundamental Component on Single-Phase EPLL and Elimination

  • Luo, Linsong;Tian, Huixin;Wu, Fengjiang
    • Journal of Power Electronics
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    • 제15권4호
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    • pp.1085-1092
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    • 2015
  • In this paper, the expressions of the estimated information of a single-phase enhanced phase-locked loop (EPLL), when input signal contains harmonics and a DC offset while the fundamental component takes step changes, are derived. The theoretical analysis results indicate that in the estimated information, the nth-order harmonics cause n+1th-order periodic ripples, and the DC offset causes a periodic ripple at the fundamental frequency. Step changes of the amplitude, phase angle and frequency of the fundamental component cause a transient periodic ripple at twice the frequency. These periodic ripples deteriorate the performance of the EPLL. A hybrid filter based EPLL (HF-EPLL) is proposed to eliminate these periodic ripples. A delay signal cancellation filter is set at the input of the EPLL to cancel the DC offset and even-order harmonics. A sliding Goertzel transform-based filter is introduced into the amplitude estimation loop and frequency estimation loop to eliminate the periodic ripples caused by the residual input odd-order harmonics and step change of the input fundamental component. The parameter design rules of the two filters are discussed in detail. Experimental waveforms of both the conventional EPLL and the proposed HF-EPLL are given and compared with each other to verify the theoretical analysis and advantages of the proposed HF-EPLL.

A novel PLL control method for robust three-phase thyristor converter under sag and notch conditions

  • Lee, Changhee;Yoo, Hyoyol
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2014년도 추계학술대회 논문집
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    • pp.87-88
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    • 2014
  • The paper presents a novel phase locked loop(PLL) control method for robust three-phase thyristor dual converters under sag, notch, and phase loss conditions. This method is applied to three line to line voltages of grid to derive three phase angle errors from three separated single-phase PLLs. They can substitute for abnormal phase to guarantee the synchronization in the various grid fault conditions. The performance of novel PLL with moving average method is verified through simulations.

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상태관측기를 이용한 단상 PLL제어의 성능 개선 (Performance Improvement of Single-phase PLL Control using State Observer)

  • 황희훈;최종우
    • 전력전자학회논문지
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    • 제14권2호
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    • pp.96-104
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    • 2009
  • 본 논문에서는 단상 전원의 위상 및 주파수 검출을 위해 전차원 상태관측기를 이용한 가상 2상 방식의 단상 위상고정루프(PLL: Phase Locked Loop) 제어기를 제안한다. 기존의 방식은 전원단에 주입된 저차 고조파를 완벽하게 제거하지 못하여 전체 PLL 시스템에 영향을 주게 된다. 제안된 알고리즘은 전차원 상태관측기를 사용하여 기본파와 고조파를 분리하고 고조파 성분을 효과적으로 제거 및 검출하여 기본파 성분만을 발생한다. 그리고 가상 발생신호 및 기존 입력신호를 함께 제어함으로써 기존방식보다 정상상태 오차를 감소시킬 수 있다. 모의실험결과 및 실제실험결과를 통하여 설계한 제어기에 의해 발생된 주파수가 실제값에 수렴하였으며 정상상태 추정 특성이 향상됨을 검증하였다. 또한 고조파 성분이 효과적으로 제거되고 기본파 성분만을 출력하는 것을 확인하였다.

Phase and Amplitude Drift Research of Millimeter Wave Band Local Oscillator System

  • Lee, Chang-Hoon;Je, Do-Heung;Kim, Kwang-Dong;Sohn, Bong-Won
    • Journal of Astronomy and Space Sciences
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    • 제27권2호
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    • pp.145-152
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    • 2010
  • In this paper, we developed a local oscillator (LO) system of millimeter wave band receiver for radio astronomy observation. We measured the phase and amplitude drift stability of this LO system. The voltage control oscillator (VCO) of this LO system use the 3 mm band Gunn oscillator. We developed the digital phase locked loop (DPLL) module for the LO PLL function that can be computer-controlled. To verify the performance, we measured the output frequency/power and the phase/amplitude drift stability of the developed module and the commercial PLL module, respectively. We show the good performance of the LO system based on the developed PLL module from the measured data analysis. The test results and discussion will be useful tutorial reference to design the LO system for very long baseline interferometry (VLBI) receiver and single dish radio astronomy receiver at the 3 mm frequency band.

D플립플롭을 사용한 작은 크기의 위상고정루프 (Small size PLL with D Flip-Flop)

  • 고기영;최혁환;최영식
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2017년도 춘계학술대회
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    • pp.697-699
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    • 2017
  • 본 논문에서는 D 플립플롭과 보조 전하펌프를 사용하여 작은 크기의 위상고정루프를 제안하였다. 단일 커패시터를 사용하여 크기가 작기 때문에 위상고정루프의 집적화가 가능하다. 제안된 위상고정루프는 HSPICE로 시뮬레이션 하였으며, 1.8V $0.18{\mu}m$ CMOS 공정을 사용하였다.

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Design and Implementation of Photovoltaic Power Conditioning System using a Current-based Maximum Power Point Tracking

  • Lee, Sang-Hoey;Kim, Jae-Eon;Cha, Han-Ju
    • Journal of Electrical Engineering and Technology
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    • 제5권4호
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    • pp.606-613
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    • 2010
  • This paper proposes a novel current-based maximum power point tracking (CMPPT) method for a single-phase photovoltaic power conditioning system (PV PCS) by using a modified incremental conductance method. The CMPPT method simplifies the entire control structure of the power conditioning system and uses an inherent current source characteristic of solar cell arrays. Therefore, it exhibits robust and fast response under a rapidly changing environmental condition. Digital phase locked loop technique using an all-pass filter is also introduced to detect the phase of grid voltage, as well as the peak voltage. Controllers of dc/dc boost converter, dc-link voltage, and dc/ac inverter are designed for coordinated operation. Furthermore, a current control using a pseudo synchronous d-q transformation is employed for grid current control with unity power factor. A 3 kW prototype PV PCS is built, and its experimental results are given to verify the effectiveness of the proposed control schemes.

계통연계형 단상 인버터의 ZVRT(Zero Voltage Ride Through)를 위한 PLL 제어 전략 (PLL Control Strategy for ZVRT(Zero Voltage Ride Through) of a Grid-connected Single-phase Inverter)

  • 이태일;이경수
    • 전력전자학회논문지
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    • 제24권3호
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    • pp.169-180
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    • 2019
  • Grid codes for grid-connected inverters are essential considerations for bulk grid systems. In particular, a low-voltage ride-through (LVRT) function, which can contribute to the grid system's stabilization with the occurrence of voltage sag, is required by such inverters. However, when the grid voltage is under zero-voltage condition due to a grid accident, a zero-voltage ride-through (ZVRT) function is required. Grid-connected inverters typically have phase-locked loop (PLL) control to synchronize the phase of the grid voltage with that of the inverter output. In this study, the LVRT regulations of Germany, the United States, and Japan are analyzed. Then, three major PLL methods of grid-connected single-phase inverters, namely, notch filter-PLL, dq-PLL using an active power filter, and second-order generalized integrator-PLL, are reviewed. The proposed PLL method, which controls inverter output under ZVRT condition, is suggested. The proposed PLL operates better than the three major PLL methods under ZVRT condition in the simulation and experimental tests.

레이다 수신기용 X-밴드 주파수 합성기의 저 위상잡음설계 및 구현 (Low Phase Noise Design and Implementation of X -Band Frequency Synthesizer for Radar Receiver)

  • 소원욱;강연덕;이택경
    • 한국항행학회논문지
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    • 제2권1호
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    • pp.22-33
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    • 1998
  • 마그네트론을 이용하는 레이다에서 송신 주파수의 변화를 감지하여 안정된 중간주파수를 발생하기 위해서는 STALO(Stable Local Oscillator)로서 AFC(Automatic Frequency Control)에 의해 출력주파수를 조정할 수 있는 주파수 합성기(Frequency Synthesizer)가 이용된다. 본 논문에서는 8.4GHz~9.7GHz의 X-밴드 주파수 합성기를 단일 루우프 구조의 간접 주파수 합성방식으로 설계하고 제작하였다. 고속 디지털 PLL 칩에 의하여 위상비교를 하고, 저 위상잡음을 구현하기 위한 여파기를 설계하였다. 기준신호와 VCO, 주파수 분주기, 여파기 등의 특성에 따른 단일 루우프 주파수 합성기의 위상잡음 성능을 해석하고, 위상잡음이 최소가 되도록 설계하여 측정치와 비교하였다.

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