• Title/Summary/Keyword: Single memory

Search Result 716, Processing Time 0.024 seconds

An Empirical Study on the Cryptocurrency Investment Methodology Combining Deep Learning and Short-term Trading Strategies (딥러닝과 단기매매전략을 결합한 암호화폐 투자 방법론 실증 연구)

  • Yumin Lee;Minhyuk Lee
    • Journal of Intelligence and Information Systems
    • /
    • v.29 no.1
    • /
    • pp.377-396
    • /
    • 2023
  • As the cryptocurrency market continues to grow, it has developed into a new financial market. The need for investment strategy research on the cryptocurrency market is also emerging. This study aims to conduct an empirical analysis on an investment methodology of cryptocurrency that combines short-term trading strategy and deep learning. Daily price data of the Ethereum was collected through the API of Upbit, the Korean cryptocurrency exchange. The investment performance of the experimental model was analyzed by finding the optimal parameters based on past data. The experimental model is a volatility breakout strategy(VBS), a Long Short Term Memory(LSTM) model, moving average cross strategy and a combined model. VBS is a short-term trading strategy that buys when volatility rises significantly on a daily basis and sells at the closing price of the day. LSTM is suitable for time series data among deep learning models, and the predicted closing price obtained through the prediction model was applied to the simple trading rule. The moving average cross strategy determines whether to buy or sell when the moving average crosses. The combined model is a trading rule made by using derived variables of the VBS and LSTM model using AND/OR for the buy conditions. The result shows that combined model is better investment performance than the single model. This study has academic significance in that it goes beyond simple deep learning-based cryptocurrency price prediction and improves investment performance by combining deep learning and short-term trading strategies, and has practical significance in that it shows the applicability in actual investment.

Development of a complex failure prediction system using Hierarchical Attention Network (Hierarchical Attention Network를 이용한 복합 장애 발생 예측 시스템 개발)

  • Park, Youngchan;An, Sangjun;Kim, Mintae;Kim, Wooju
    • Journal of Intelligence and Information Systems
    • /
    • v.26 no.4
    • /
    • pp.127-148
    • /
    • 2020
  • The data center is a physical environment facility for accommodating computer systems and related components, and is an essential foundation technology for next-generation core industries such as big data, smart factories, wearables, and smart homes. In particular, with the growth of cloud computing, the proportional expansion of the data center infrastructure is inevitable. Monitoring the health of these data center facilities is a way to maintain and manage the system and prevent failure. If a failure occurs in some elements of the facility, it may affect not only the relevant equipment but also other connected equipment, and may cause enormous damage. In particular, IT facilities are irregular due to interdependence and it is difficult to know the cause. In the previous study predicting failure in data center, failure was predicted by looking at a single server as a single state without assuming that the devices were mixed. Therefore, in this study, data center failures were classified into failures occurring inside the server (Outage A) and failures occurring outside the server (Outage B), and focused on analyzing complex failures occurring within the server. Server external failures include power, cooling, user errors, etc. Since such failures can be prevented in the early stages of data center facility construction, various solutions are being developed. On the other hand, the cause of the failure occurring in the server is difficult to determine, and adequate prevention has not yet been achieved. In particular, this is the reason why server failures do not occur singularly, cause other server failures, or receive something that causes failures from other servers. In other words, while the existing studies assumed that it was a single server that did not affect the servers and analyzed the failure, in this study, the failure occurred on the assumption that it had an effect between servers. In order to define the complex failure situation in the data center, failure history data for each equipment existing in the data center was used. There are four major failures considered in this study: Network Node Down, Server Down, Windows Activation Services Down, and Database Management System Service Down. The failures that occur for each device are sorted in chronological order, and when a failure occurs in a specific equipment, if a failure occurs in a specific equipment within 5 minutes from the time of occurrence, it is defined that the failure occurs simultaneously. After configuring the sequence for the devices that have failed at the same time, 5 devices that frequently occur simultaneously within the configured sequence were selected, and the case where the selected devices failed at the same time was confirmed through visualization. Since the server resource information collected for failure analysis is in units of time series and has flow, we used Long Short-term Memory (LSTM), a deep learning algorithm that can predict the next state through the previous state. In addition, unlike a single server, the Hierarchical Attention Network deep learning model structure was used in consideration of the fact that the level of multiple failures for each server is different. This algorithm is a method of increasing the prediction accuracy by giving weight to the server as the impact on the failure increases. The study began with defining the type of failure and selecting the analysis target. In the first experiment, the same collected data was assumed as a single server state and a multiple server state, and compared and analyzed. The second experiment improved the prediction accuracy in the case of a complex server by optimizing each server threshold. In the first experiment, which assumed each of a single server and multiple servers, in the case of a single server, it was predicted that three of the five servers did not have a failure even though the actual failure occurred. However, assuming multiple servers, all five servers were predicted to have failed. As a result of the experiment, the hypothesis that there is an effect between servers is proven. As a result of this study, it was confirmed that the prediction performance was superior when the multiple servers were assumed than when the single server was assumed. In particular, applying the Hierarchical Attention Network algorithm, assuming that the effects of each server will be different, played a role in improving the analysis effect. In addition, by applying a different threshold for each server, the prediction accuracy could be improved. This study showed that failures that are difficult to determine the cause can be predicted through historical data, and a model that can predict failures occurring in servers in data centers is presented. It is expected that the occurrence of disability can be prevented in advance using the results of this study.

A Study of NMEA Protocol Multiplexer Simulation on the based optimizing Queue (최적화된 큐 기반의 NMEA 프로토콜 멀티플렉서 시뮬레이션에 관한 연구)

  • Park Si-Hyoung;Jung Sung-Hun;Kim Chang-Soo;Yim Chang-Mook;Yim Jae-Hong
    • Proceedings of the Korean Institute of Navigation and Port Research Conference
    • /
    • 2004.11a
    • /
    • pp.15-19
    • /
    • 2004
  • Domestic use, or embody program that transmit NMEA protocol using multi port as software and is using because there is no fee and product that develop NMEA protocol Multiplexer, import mounting for foreign climax present. These method is paid or there is problem that must make out special processing part in each application program. Also, each mountings that display NMEA protocol can cause double resources waste and damage etc. because manufacturing firm and platform are different. Can act separatively as single hardware module of reliable processing method and high efficiency to supplement this in this treatise, and because using design of optimized cue, heighten memory efficiency of module, and proposed NMEA protocol Multiplexer that can keep high trustability of Come on, deviation compass, echo sound, mountings of GPS and so on and real time communication that is main input sensor equipment about embodiment.

  • PDF

A New Pipelined Binary Search Architecture for IP Address Lookup (IP 어드레스 검색을 위한 새로운 pipelined binary 검색 구조)

  • Lim Hye-Sook;Lee Bo-Mi;Jung Yeo-Jin
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.29 no.1B
    • /
    • pp.18-28
    • /
    • 2004
  • Efficient hardware implementation of address lookup is one of the most important design issues of internet routers. Address lookup significantly impacts router performance since routers need to process tens-to-hundred millions of packets per second in real time. In this paper, we propose a practical IP address lookup structure based on the binary tree of prefixes of different lengths. The proposed structure produces multiple balanced trees, and hence it solve the issues due to the unbalanced binary prefix tree of the existing scheme. The proposed structure is implemented using pipelined binary search combined with a small size TCAM. Performance evaluation results show that the proposed architecture requires a 2000-entry TCAM and total 245 kbyte SRAMs to store about 30,000 prefix samples from MAE-WEST router, and an address lookup is achieved by a single memory access. The proposed scheme scales very well with both of large databases and longer addresses as in IPv6.

Design of an Encoding-Decoding System using Majority-Logic Decodable Circuits of Reed-Muller Code (다수논리 결정자를 이용한 리드뮬러코드의 시스템 설계)

  • 김영곤;강창언
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.10 no.5
    • /
    • pp.209-217
    • /
    • 1985
  • Using the Reed-Muller Codes, the encoder and decoder system has been designed and tested in this paper. The error correcting capability of this code is [J/2} or less and the error correcting procedure can be implemented easily by using simple logic circuitry. The encoding and decoding circuits are obtained by the cyclic property and for the O15, 11) Reed-Muller code majority-logic decoding is taken. The performance is measured in error probability and weight destribution. The encoder and decoder system has been designed, implemented and interfaced with the microcomputer by using the 8255 chip. Experimental results show that the system has single error-correcting capability and total execution time for a data is about 70usec. When the probability of channel error is $10^{-6}$~$10^{-4}$ the system using the (15, 11) Reed-Muller code works very good.

  • PDF

EEPROM Charge Sensors (EEPROM을 이용한 전하센서)

  • Lee, Dong-Kyu;Jin, Hai-Feng;Yang, Byung-Do;Kim, Young-Suk;Lee, Hyung-Gyoo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.23 no.8
    • /
    • pp.605-610
    • /
    • 2010
  • The devices based on electrically erasable programmable read-only memory (EEPROM) structure are proposed for the detection of external electric charges. A large size charge contact window (CCW) extended from the floating gate is employed to immobilize external charges, and a control gate with stacked metal-insulator-metal (MIM) capacitor is adapted for a standard single polysilicon CMOS process. When positive voltage is applied to the capacitor of CCW of an n-channel EEPROM, the drain current increases due to the negative shift of its threshold voltage. Also when a pre-charged external capacitor is directly connected to the floating gate metal of CCW, the positive charges of the external capacitor make the drain current increase for n-channel, whereas the negative charges cause it to decrease. For an p-channel, however, the opposite behaviors are observed by the external voltage and charges. With the attachment of external charges to the CCW of EEPROM inverter, the characteristic inverter voltage behavior shifts from the reference curve dependent on external charge polarity. Therefore, we have demonstrated that the EEPROM inverter is capable of detecting external immobilized charges on the floating gate. and these devices are applicable to sensing the pH's or biomolecular reactions.

Damage detection in plate structures using frequency response function and 2D-PCA

  • Khoshnoudian, Faramarz;Bokaeian, Vahid
    • Smart Structures and Systems
    • /
    • v.20 no.4
    • /
    • pp.427-440
    • /
    • 2017
  • One of the suitable structural damage detection methods using vibrational characteristics are damage-index-based methods. In this study, a damage index for identifying damages in plate structures using frequency response function (FRF) data has been provided. One of the significant challenges of identifying the damages in plate structures is high number of degrees of freedom resulting in decreased damage identifying accuracy. On the other hand, FRF data are of high volume and this dramatically decreases the computing speed and increases the memory necessary to store the data, which makes the use of this method difficult. In this study, FRF data are compressed using two-dimensional principal component analysis (2D-PCA), and then converted into damage index vectors. The damage indices, each of which represents a specific condition of intact or damaged structures are stored in a database. After computing damage index of structure with unknown damage and using algorithm of lookup tables, the structural damage including the severity and location of the damage will be identified. In this study, damage detection accuracy using the proposed damage index in square-shaped structural plates with dimensions of 3, 7 and 10 meters and with boundary conditions of four simply supported edges (4S), three clamped edges (3C), and four clamped edges (4C) under various single and multiple-element damage scenarios have been studied. Furthermore, in order to model uncertainties of measurement, insensitivity of this method to noises in the data measured by applying values of 5, 10, 15 and 20 percent of normal Gaussian noise to FRF values is discussed.

Test-case Generation for Simulink/Stateflow Model using a Separated RRT Space (분할된 RRT 공간을 이용한 Simulink/Stateflow모델 테스트케이스 생성)

  • Park, Hyeon Sang;Choi, Kyung Hee;Chung, Ki Hyun
    • KIPS Transactions on Software and Data Engineering
    • /
    • v.2 no.7
    • /
    • pp.471-478
    • /
    • 2013
  • This paper proposes a black-box based test case generation method for Simulink/Stateflow model utilizing the RRT algorithm which is a method to efficiently solve the path planning for complicated systems. The proposed method in the paper tries to solve the reachability problem with the RRT algorithm, which has to be solved for black-box based test case generations. A major problem of the RRT based test case generation algorithms is that the cost such as running time and required memory size is too much for complicated Stateflow model. The typical RRT algorithm expands rapidly-exploring random tree (RRT) in a single state space. But the proposed method expands it in dynamic state space based on the state of Simulink model, consequently reducing the cost. In the paper, a new definition of RRT state space, a distance measure and a test case generation algorithm are proposed. The performance of proposed method is verified through the experiment against Stateflow model.

A Reconfigurable Load and Performance Balancing Scheme for Parallel Loops in a Clustered Computing Environment (클러스터 컴퓨팅 환경에서 병렬루프 처리를 위한 재구성 가능한 부하 및 성능 균형 방법)

  • 김태형
    • Journal of KIISE:Computing Practices and Letters
    • /
    • v.10 no.1
    • /
    • pp.49-56
    • /
    • 2004
  • Load imbalance is a serious impediment to achieving good performance in parallel processing. Global load balancing schemes cannot adequately manage to balance parallel tasks generated from a single application. Dynamic loop scheduling methods are known to be useful in balancing parallel loops on shared-memory multiprocessor machines. However, their centralized nature causes a bottleneck for the relatively small number of processors in a network of workstations because of order-of-magniture differences in communication overheads. Moreover, improvements of basis loops scheduling methods have not effectively dealt with irregularly distributed workloads in parallel loops, which commonly occur in applications for a network of workstation. In this paper, we present a new reconfigurable and decentralized balancing method for parallel loops on a network of workstations. Since our method supplements performance balancing with those tranditional load balancing methods, it minimizes the overall execution time.

A Study on SoC Platform Design Supporting Dynamic Cooperation between Hardware and Software Modules (하드웨어 및 소프트웨어 모듈간의 동적 협업을 지원하는 SoC 플랫폼 설계에 관한 연구)

  • Lee, Dong-Geon;Kim, Young-Mann;Tak, Sung-Woo
    • Journal of Korea Multimedia Society
    • /
    • v.10 no.11
    • /
    • pp.1446-1459
    • /
    • 2007
  • This paper presents and analyzes a novel technique that makes it possible to improve the performance of low-end embedded systems through SoC(System-on-a-Chip) platform supporting dynamic cooperation between hardware and software modules. Traditional embedded systems with limited hardware resources have the poor capability of carrying out multi-tasking jobs including complex calculations. The proposed SoC platform, which provides dynamic cooperation between hardware and software modules, decomposes a single specific system into tasks for given system requirements. Additionally, we also propose a technique for efficient communication and synchronization between hardware and software tasks in cooperation with each other. Several experiments are conducted to illustrate the application and efficiency of the proposed SoC platform. They show that the proposed SoC platform outperforms the traditional embedded system, where only software tasks run, as the number of memory access is increased and the system become more complex.

  • PDF