• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.07a
• /
• pp.751-754
• /
• 2000

When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.

• The Transactions of the Korea Information Processing Society
• /
• v.3 no.6
• /
• pp.1433-1442
• /
• 1996

Data distribution of SPMD(Single Program Multiple Data) pattern is one of main features of HPF (High Performance Fortran). This paper describes design is sues for such data distribution and its efficient execution model on TICOM IV computer, named SPAX(Scalable Parallel Architecture computer based on X-bar network). SPAX has a hierarchical clustering structure that uses distributed shared memory(DSM). In such memory structure, it cannot make a full system utilization to apply unanimously either SMDD(shared Memory Data Distribution) or DMDD(Distributed Memory Data Distribution). Here we propose another data distribution model, called DSMDD(Distributed Shared Memory Data Distribution), a data distribution model based on hierarchical masters-slaves scheme. In this model, a remote master and slaves are designated in each node, shared address scheme is used within a node and message passing scheme between nodes. In our simulation, assuming a node size in which system performance degradation is minimized,DSMDD is more effective than SMDD and DMDD. Especially,the larger number of logical processors and the less data dependency between distributed data,the better performace is obtained.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.8 no.1
• /
• pp.66-79
• /
• 2008

Several oxides have recently been reported to have resistance-switching characteristics for nonvolatile memory (NVM) applications. Both binary and ternary oxides demonstrated great potential as resistive-switching memory elements. However, the switching mechanisms have not yet been clearly understood, and the uniformity and reproducibility of devices have not been sufficient for gigabit-NVM applications. The primary requirements for oxides in memory applications are scalability, fast switching speed, good memory retention, a reasonable resistive window, and constant working voltage. In this paper, we discuss several materials that are resistive-switching elements and also focus on their switching mechanisms. We evaluated non-stoichiometric polycrystalline oxides ($Nb_2O_5$, and $ZrO_x$) and subsequently the resistive switching of $Cu_xO$ and heavily Cu-doped $MoO_x$ film for their compatibility with modem transistor-process cycles. Single-crystalline Nb-doped $SrTiO_3$ (NbSTO) was also investigated, and we found a Pt/single-crystal NbSTO Schottky junction had excellent memory characteristics. Epitaxial NbSTO film was grown on an Si substrate using conducting TiN as a buffer layer to introduce single-crystal NbSTO into the CMOS process and preserve its excellent electrical characteristics.

• Journal of The Korean Society of Integrative Medicine
• /
• v.9 no.4
• /
• pp.91-103
• /
• 2021

Purpose : This study aimed to evaluate the effects of a cognitive enhancement brain yoga program on short-term memory and serum brain-derived neurotrophic factor (BDNF) levels according to the cognitive state in men aged 20-29 years. Methods : Thirty healthy volunteers aged 20-29 years were divided into four groups: brain yoga group, yoga group, combined exercise group, and control group. Seven people were assigned randomly per group. A single-session intervention was conducted over 50 min and consisted of three parts: warm-up, main exercise (brain yoga, yoga, combined exercise, or non-exercise), and cool-down. Serum BDNF levels were measured using enzyme-linked immunosorbent assay, and short-term memory was evaluated using the forward number span test before and after the intervention. Results : BDNF levels significantly increased within the brain yoga group after the intervention (from 28874.37±5185.57 to 34074.80±7321.12, p=.003), whereas there were no significant differences pre-and post-intervention in the other groups. The inter-group comparison showed a significant interaction between the brain yoga group and the combined exercise group (p=.036) but no significant interaction between any of the other groups. Forward number span scores were significantly increased in the brain yoga group (from 9.43±9.83 to 23±7.92, p=.012) and theyoga group after the intervention (from 13.43±9.41 to 24.14±8.45, p=.011), whereas there were no significant changes after the intervention in any other groups. Conclusion : Our findings showed that a single-session, 50-minute brain yoga exercise improved short-term memory and increased serum BDNF levels in healthy men aged 20-29 years and that yoga improved only short-term memory in healthy men of this age group.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.19 no.11
• /
• pp.994-999
• /
• 2006

For low-cost embedded EEPROM, in this paper, single polysilicon EEPROM and n-channel high-voltage LDMOST device are developed in a $0.25{\mu}m$ standard CMOS logic process. Using these devices developed, the EEPROM chip is fabricated. The fabricated EEPROM chip is composed of 1 Kbit single polysilicon EEPROM away and high voltage driver circuits. The program and erase characteristics of the fabricated EEPROM chip are evaluated using 'STA-EL421C'. The fabricated n-channel high-voltage LDMOST device operation voltage is over 10 V and threshold voltage window between program and erase states of the memory cell is about 2.0 V.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.8
• /
• pp.23-32
• /
• 1998

In this paper, we propose a memory compiler to genrate embedded RAMs and ROMs for ASIC chips. We design the leaf cells to be compsoed of memory blocks. The compiler is built using tile-based method to simplify routing. The compiler can genrate any memory layouts to satisfy 64 to 4096 words and 4 to 256 bits per word. The technology we used here is 0.8.mu.m single poly double metal CMOS process. The address access time and power consumption are verifie dthrough the HSPICE simulation.

• Journal of Ginseng Research
• /
• v.20 no.3
• /
• pp.226-232
• /
• 1996

This study was performed to investigate the effect of red ginseng extract including some vitamin B groups as test drug on learning and memory in mice. Single and repeated administrations of the test drug improved the acquisition and the process of consolidation in the tests using step-through and step-down apparatus, indicating this test drug improved learning and memory. However, the test drug did not improve scopolamine-induced amnesia. These results suggest that test drug may be useful as a nootropic agent.

• Nuclear Engineering and Technology
• /
• v.49 no.8
• /
• pp.1589-1599
• /
• 2017

Field programmable gate arrays (FPGAs) are getting more attention in safety-related and safety-critical application development of nuclear power plant instrumentation and control systems. The high logic density and advancements in architectural features make static random access memory (SRAM)-based FPGAs suitable for complex design implementations. Devices deployed in the nuclear environment face radiation particle strike that causes transient and permanent failures. The major reasons for failures are total ionization dose effects, displacement damage dose effects, and single event effects. Different from the case of space applications, soft errors are the major concern in terrestrial applications. In this article, a review of radiation effects on FPGAs is presented, especially soft errors in SRAM-based FPGAs. Single event upset (SEU) shows a high probability of error in the dependable application development in FPGAs. This survey covers the main sources of radiation and its effects on FPGAs, with emphasis on SEUs as well as on the measurement of radiation upset sensitivity and irradiation experimental results at various facilities. This article also presents a comparison between the major SEU mitigation techniques in the configuration memory and user logics of SRAM-based FPGAs.

• Journal of Korea Multimedia Society
• /
• v.19 no.7
• /
• pp.1179-1187
• /
• 2016

Through the rapid development of latest hardware technology, high performance as well as miniaturized size is the essentials of embedded system to meet various requirements from the society. It raises possibilities of genuine realization of IoT environment whose size and battery must be considered. However, the limitation of battery persistency and capacity restricts the long battery life time for guaranteeing real-time system. To maximize battery life time, low power technology which lowers the power consumption should be highly required. Previous researches mostly highlighted improving one single type of memory to increase ones efficiency. In this paper, reversely, considering multiple memories to optimize whole memory system is the following step for the efficient low power embedded system. Regarding to that fact, this paper suggests the study of volatile memory, whose capacity is relatively smaller but much low-powered, and non-volatile memory, which do not consume any standby power to keep data, to maximize the efficiency of the system. By executing function in specific memories, non-volatile and volatile memory, the quantitative analysis of power consumption is progressed. In spite of the opportunity cost of all of theses extra works to locate function in volatile memory, higher efficiencies of both power and energy are clearly identified compared to operating single non-volatile memory.

• Journal of KIISE:Computing Practices and Letters
• /
• v.11 no.6
• /
• pp.477-487
• /
• 2005

As embedded system grows in size and complexity, the importance of the technique for dynamic memory allocation has increased. The objective of this paper is to measure the performance of dynamic memory allocation by varying both hardware and software design parameters for embedded systems. Unlike torrent performance evaluation studies that have presumed the single threaded system with single address spate without OS support, our study adopts realistic environment where the embedded system runs on Linux OS. This paper contains the experimental performance analyses of dynamic memory allocation method by investigating the effects of each software layer and some hardware design parameters. Our quantitative results tan be used to help system designers design high performance, low power embedded systems.