• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.6
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• pp.703-709
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• 2014

In the AMP(Asymmetric Multiprocessing) based dual core using core-specific operating system in a single processor system, shared memory method is used to send data between processors in dual core. To used shared memory in different operating systems, there is a problem of needing to solving the issue of message communication and synchronization between the two operations systems. In this paper, separate memory controller was used for data sharing between different processor cores in dual core environment. This controller can designate two slave ports to allow simultaneous access from two processors, and in the case of process data simultaneously by two processors, priority order of slave ports is determined through memory mediator. When sending data from A to B processor, SRAM area was logically separated into 8 pages. It allowed using memory area from multiple processes with the size of 4KByte per page, and control register with the size of 4Byte was used to discern the usability of current page.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.608-611
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• 2003

A large part of the embedded system, compared with the PC, have low performance CPU and small memory. So the embedded operating system fits the condition of that hardware system. A Single Address Space (SAS) OS has the operating system and all applications in the single address space. The SAS architecture enhances sharing and co-operation, because addresses have a unique interpretation. Thus, pointer-based date structures can be directly communicated and shared between programs at any time, and can be stored directly on storage. The key point of the SAS OS on the embedded system is the low overhead inter-action between programs in process and usage. So SAS OS can be ported on the low performance CPU. In this paper, we design the SAS OS (named emNOS, Embedded Network Operating System) on the ARMTTDMI processor. Finally we show the benefits of the SAS OS on the embedded system.

• ETRI Journal
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• v.46 no.3
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• pp.501-512
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• 2024

With an explosive increase of data produced annually, researchers have been attempting to develop solutions for systems that can effectively handle large amounts of data. Single-operating-system (OS) non-uniform memory access (NUMA) abstraction technology is an important technology that ensures the compatibility of single-node programming interfaces across multiple nodes owing to its higher cost efficiency compared with scale-up systems. However, existing technologies have not been successful in optimizing user performance. In this paper, we introduce a single-OS NUMA abstraction technology that ensures full compatibility with the existing OS while improving the performance at both hypervisor and guest levels. Benchmark results show that the proposed technique can improve performance by up to 4.74× on average in terms of execution time compared with the existing state-of-the-art opensource technology.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.91-95
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• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.

• Journal of the Korea Society of Computer and Information
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• v.25 no.3
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• pp.51-55
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• 2020

In this paper, an improved FAM is proposed by adopting similarity learning in the existing FAM (Fuzzy Associative Memory) used in image restoration. Image restoration refers to the recovery of the latent clean image from its noise-corrupted version. In serious application like face recognition, this process should be noise-tolerant, robust, fast, and scalable. The existing FAM is a simple single layered neural network that can be applied to this domain with its robust fuzzy control but has low capacity problem in real world applications. That similarity measure is implied to the connection strength of the FAM structure to minimize the root mean square error between the recovered and the original image. The efficacy of the proposed algorithm is verified with significant low error magnitude from random noise in our experiment.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.12
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• pp.1199-1203
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• 2010

Data transfer between host system and storage device is based on the data unit called sector, which can be varied depending on computer systems. If NAND flash memory is used as a storage device, the variant sector size can affect storage system performance since its operation is much related to sector size and page size. In this paper, we propose an efficient FTL mapping management scheme to support multiple sector size within one NAND flash memory based storage device, and analyze the performance effect and management overhead. According to the proposed scheme, the management overhead of proposed FTL management is lower than conventional scheme when various sector sizes are configured in computer systems, while performance is less degraded in comparison with single sector size support system.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.1
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• pp.53-59
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• 2008

In spite of increasing complexity of wireless sensor network applications, most of the sensor node platforms still have severe resource constraints. Especially a small amount of memory and absence of a memory management unit (MMU) cause many problems in managing application thread stacks. Hence, a shared-stack was proposed, which allows several threads to share one single stack for minimizing the amount of memory wasted by fixed-size stacks. In this paper, we present the memory usage models for thread stacks by deriving the overflow probability of the fixed-size stack and the shared-stack and also show that the shared-stack is more reliable than the fixed-size stack.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.305-309
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• 2002

We have successfully fabricated a Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure using Bi$\sub$4-x/La$\sub$x/Ti$_3$O$\sub$12/ (BLT) ferroelectric thin film and SiO$_2$/Nitride/SiO$_2$ (ONO) stacked buffer layers for single transistor type ferroelectric nonvolatile memory applications. BLT films were deposited on 15 nm-thick ONO buffer layer by sol-gel spin-coating. The dielectric constant and the leakage current density of prepared ONO film were measured to be 5.6 and 1.0 x 10$\^$-8/ A/$\textrm{cm}^2$ at 2MV/cm, respectively, It was interesting to note that the crystallographic orientations of BLT thin films were strongly effected by pre-bake temperatures. X-ray diffraction patterns showed that (117) crystallites were mainly detected in the BLT film if pre-baked below 400$^{\circ}C$. Whereas, for the films pre-baked above 500$^{\circ}C$, the crystallites with preferred c-axis orientation were mainly detected. From the C-V measurement of the MFIS capacitor with c-axis oriented BLT films, the memory window of 0.6 V was obtained at a voltage sweep of ${\pm}$8 V, which evidently reflects the ferroelectric memory effect of a BLT/ONO/Si structure.

• Transactions of the Society of Information Storage Systems
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• v.7 no.2
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• pp.53-59
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• 2011

We have developed a compact and high-power mode-locked fiber laser for multilayered optical memory. Fiber lasers have the potential to be compact and stable light sources that can replace bulk solid-state lasers. To generate high-power pulses, we used stretched-pulse mode locking. The average power and pulse width of the output pulse from the fiber laser that we developed were 109 mW and 2.1 ps, respectively. The dispersion of the output pulse was compensated with an external single-mode fiber of 2.5 m length. The pulse was compressed from 2.1 ps to 93 fs by dispersion compensation. The fiber laser we have developed is possible to use as a light source of multilayered optical memory. We also present a fiber confocal microscope as an alignment-free readout system of multilayered optical memories. The fiber confocal microscope does not require fine pinhole position alignment because the fiber core is used as the point light source and the pinhole, and both of which are always located at the conjugated point. The configuration reduces the required accuracy of pinhole position alignment. With these techniques we can present an all-fiber recording and readout system for multilayered memories.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.72-79
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• 2003

Due to the improvements in circuit design technique and manufacturing technique, complexity of a circuit is growing along with the demand for memories with large capacities. Likewise, as a memory capacity gets larger, testing gets harder and testing cost increases, and testing process in chip development gets larger as well. Therefore, a research on an effective test algorithm to improve the chip yield rate in a short time period is becoming an important task. This paper proposes an effective, March C-algorithm based, test algorithm that can also be applied to a dual-port memory since it considers all the fault types, which can be occurred in a single-port as well as in a dual-port memory, without increasing the test length.