• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.540-543
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• 2010

POWER PC series are common to the Central Processing Unit for Military Single Board Computer. Among them, G4 group, which contains the 74xx series supported by Freescale manufacturer is mainly used in the Military applications. We focus on the Interface between memory and controller. PCB stacking method, component routing, impedance matching and harsh environment for Military spec are the main constraints for implementation. Also, we developed memory as a module for the consideration of Military environments. The overall type of SBC should be designed by the form of 6U VME or 3U VME.

• Nuclear Engineering and Technology
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• v.56 no.8
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• pp.2916-2922
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• 2024

\\In memory semiconductors such as a static random access memory (SRAM), a common problem is soft errors under radiation environment. These soft errors cause bit flips, which are referred to as single event upsets (SEUs). Some radiation-hardened SRAM cells such as a Quatro SRAM, we-Quatro SRAM, and DICE SRAM cells have been reported for years. However, these designs have the disadvantage of taking up more area than a conventional 6T SRAM cell. Thus, we propose a radiation-hardened SRAM cell design that we named capacitor-static random access memory (C-SRAM) without area overhead. The C-SRAM is formed by simply adding a capacitor to the conventional 6T SRAM. It was designed to mitigate the radiation effect using the conservation law of electrical charge. Moreover, it has the same cell size as the conventional 6T SRAM cell. Its static noise margins (SNMs), which are indicators of operational stability, are equal to the conventional 6T SRAM values of 530 mV, 220 mV, and 860 mV in hold, read, and write modes, respectively. The results of the SEU simulation test showed that it had 4.761 times better flipping tolerance than the conventional 6T SRAM with a charge value of 247.494 fC. In addition, irradiation experiments also confirmed that the C-SRAM cell was more tolerant than the 6T SRAM cell. The conventional 6T SRAM and C-SRAM were fabricated using a standard 0.18 ㎛ CMOS process.

• Korean Journal of Cognitive Science
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• v.11 no.3_4
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• pp.33-43
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• 2000

The distinction between short-term store (STS) and long-term store (LTS) has been made in the perspective of information processing. Memory system theorists have argued that memory could be conceived as multiple memory systems beyond the concept of a single LTS. Popular memory system models are Schacter & Tulving (994)'s multiple memory systems and Squire (987)'s the taxonomy of long-term memory. Those m models agree that amnesic patients have intact STS but impaired LTS and have preserved implicit memory. However. there is a debate about the nature of the long-term memory impairment. One model considers amnesic deficit as a selective episodic memory impairment. whereas the other sees the deficits as both episodic and semantic memory impairment. At present, it remains unclear that episodic memory should be distinguished from semantic memory in terms of retrieval operation. The distinction between declarative memory and nondeclarative memory would be the alternative way to reflect explicit memory and implicit memory. The research focused on the function of frontal lobe might give clues to the debate about the nature of LTS.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.187-190
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• 2005

There have been many studies to improve the performance of a database system focused on modifying data structure, data partitioning, and materializing strategy. The main contribution of this study is to propose a new alternative towards improving database performance by designing single table schema or processing queries virtually in main memory space. Material Requirement Planning(MRP) part explosion process has shown almost 2 times shorter under DB schema we suggested, and even more than 10 times shorter when separating and filtering policy of DB archiving process are assumed. Several experimental results are shown to illustrate the excellence of our solution.

• Applied Science and Convergence Technology
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• v.26 no.5
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• pp.129-132
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• 2017

We report a chemical vapor deposition approach and optimized growth condition to the synthesis of single layer molybdenum disulfide ($MoS_2$). Obtaining large grain size with continuous $MoS_2$ atomically thin films is highly responsible to the growth distance between molybdenum trioxide source and receiving silicon substrate. Experimental results indicate that triangular shape $MoS_2$ grain size could be enlarged up to > 80um with the precisely controlled the source-to-substrate distance under 7.5 mm. Furthermore, we demonstrate fabrication of a memory device by employing poly(methyl methacrylate) (PMMA) as insulating layer. The fabricated devices have a PMMA-$MoS_2$/metal configuration and exhibit a bistable resistance switching behavior with high/low-current ratio around $10^3$.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.8
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• pp.1440-1446
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• 2008

In this paper, a novel TMR (Triple Modular Redundancy) memory structure is proposed using state feedback control of asynchronous sequential machines. The main ability of the proposed structure is to correct the fault of SEU (Single Event Upset) asynchronously without resorting to the global synchronous clock. A state-feedback controller is combined with the TMR realized as a closed-loop asynchronous machine and corrective behavior is operated whenever an unauthorized state transition is observed so as to recover the failed state of the asynchronous machine to the original one. As a case study, an asynchronous machine modelling of TMR and the detailed procedure of controller construction are presented. A simulation results using VHDL shows the validity of the proposed scheme.

• Journal of Sensor Science and Technology
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• v.12 no.1
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• pp.51-56
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• 2003

We describe a charge pump circuit using VCO (voltage controlled oscillator) for storing information into local memories in neural networks. The VCO is used for adjusting the output voltage of the charge pump to the reference voltage and for reducing the fluctuation generated by the clocking scheme. The charge pump circuit is simulated by using Hynix 0.35um CMOS process parameters. The proposed charge pump operates properly regardless to the temperature and the supply voltage variation.

• Proceedings of the KSME Conference
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• 2004.04a
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• pp.706-709
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• 2004

A numerical method was developed that imposes constraint condition on the order parameters in martensitic phase transformation. In the method, an amplitude function having values of 1 or 0 was multiplied to transformation rates. The merit of the method is that the imposition of the constraint condition is more straightforward than a method with Lagrangian multiplier and easy to implement in the tangent modulus method. The developed method is applied to three-dimensional finite element analyses of single and poly crystalline shape memory alloys.

• Journal of Digital Contents Society
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• v.15 no.5
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• pp.631-642
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• 2014

The main memory DBMS is operated which the contents of the table that resides on a disk at the same time as the drive is in the memory. However, because the main memory DBMS stores the data and transaction log file using the disk file system, there are a limit to the speed at which the CPU accesses the memory. In this paper, I evaluated the performance through analysis of the application side difference the technology that has been implemented in Altibase system of main memory DBMS and Sybase of disk-based DBMS. When the application performance of main memory DBMS is in comparison with the disk-based DBMS, the performance of main memory DBMS was outperformed 1.24~3.36 times in the single soccer game, and was outperformed 1.29~7.9 times in the soccer game / special soccer. The result of sale transaction response time showed a fast response time of 1.78 ~ 6.09 times.

• The Journal of Korean Academy of Sensory Integration
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• v.14 no.1
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• pp.19-30
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• 2016

Objective : The purpose of this study was to identify the effects of Interactive Metronome (IM) training on short-term memory and attention for children with mental retardation. Methods : For this study, single-subject experimental research was conducted using an ABA design. We observed two children, twice a week for 9 weeks, which was 18 sessions in total. We evaluated the children's brain waves without intervention and the child's pseudo randomly selected sample of one short-term memory task as assessed in the baseline A phase for three sessions. In the intervention phase the children received 40-50 minutes of Interactive Metronome training twice a week, a total of 12 sessions. The short-term memory test and long form test as assessed after treatment, without brain wave in short form test measuring. During the baseline A phase, data were collected using the same procedure as the baseline A phase. Results : After the interactive metronome training, positive changes was observed in brain waves, attentions and short-term memory. Conclusion : The results of this study expect that IM training has a potential for improving cognitive functions of children with mental retardation. In addition, the results of this study can be used as basic data in attention and short-term memory of occupational therapy intervention for children with mental retardation.