• Transactions on Electrical and Electronic Materials
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• v.16 no.3
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• pp.156-161
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• 2015

In this paper, we present simulation results obtained using SILVACO TCAD tools for a 3-D silicon on insulator (SOI) n-FinFET structure with a gate length of 8 nm at 300K. The effects of variations of the device’s key electrical parameters, such as threshold voltage, subthreshold slope, transconductance, drain induced barrier lowering, oncurrent, leakage current and on/off current ratio are presented and analyzed. We will also describe some simulation results related to the influence of the gate work function variations on the considered structure. These variations have a direct impact on the electrical device characteristics. The results show that the threshold voltage decreases when we reduce the gate metal work function Φ_m. As a consequence, the behavior of the leakage current improves with increased Φ_m. Therefore, the short channel effects in real 3-D FinFET structures can reasonably be controlled and improved by proper adjustment of the gate metal work function.

• 한국신재생에너지학회:학술대회논문집
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• 2011.11a
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• pp.57.2-57.2
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• 2011

Dye-sensitized solar cells (DSSC) have recently been developed as a cost-effective photovoltaic system due to their low-cost materials and facile processing. The production of DSSC involves chemical and thermal processes but no vacuum is involved. Therefore, DSSC can be fabricated without using expensive equipment. The use of dyes and nanocrystalline $TiO_2$ is one of the most promising approaches to realize both high performance and low cost. The efficiency of the DSSC changes consequently in the particle size, morphology, crystallization and surface state of the $TiO_2$. Nanocrystalline $TiO_2$ materials have been widely used as a photo catalyst and an electron collector in DSSC. Front electrode in DSSC are required to have an extremely high porosity and surface area such that the dyes can be sufficiently adsorbed and be electronically interconnected, resulting in the efficient generation of photocurrent within cells. In this study, DSSC were fabricated by an screen printing for the $TiO_2$ thin film. $TiO_2$ nanoparticles characterized by X-ray diffractometer (XRD) and scanning electron microscope (SEM) and scanning auger microscopy (SAM) and zeta potential and electrochemical impedance spectroscopy(EIS).In addition, DSSC module was modeled and simulated using the SILVACO TCAD software program. Improve the efficiency of DSSC, the effect of $TiO_2$ thin film thickness and $TiO_2$ nanoparticle size was investigated by SILVACO TCAD software program.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.605-608
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• 2004

A $Pt/Al_xGa_{l-x}N$ Schottky type Ultra-violet photodetector was modeled and simulated using the commercial SILVACO software program. In the carrier transport, we applied field model and other analytic model to determine the electron saturation velocity and low field mobility for GaN and $Al_xGa_{l-x}N$. A C-Interpreter function was defined to described the mole-fraction for the ternary compound semiconductor such as $Al_xGa_{l-x}N$. As comparing the simulated and experimental results, we found that the simulated result for type-1 has $15.9 nA/cm^2$ of leakage current at 5V. We confirmed a good agreement of photo-current in the UV Photo-detector, while applying the absorption coefficient and reflective index of active $Al_xGa_{l-x}N$ and other layers. There had been an intensive search for the proper refractive indices of the layers.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.329-334
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• 2016

In this work, the temperature dependence of electrical parameters of nanoscale SOI (silicon-on-insulator) TG (triple gate) n-FinFET (n-channel Fin field effect transistor) was investigated. Numerical device simulator $ATLAS^{TM}$ was used to construct, examine, and simulate the structure in three dimensions with different models. The drain current, transconductance, threshold voltage, subthreshold swing, leakage current, drain induced barrier lowering, and on/off current ratio were studied in various biasing configurations. The temperature dependence of the main electrical parameters of a SOI TG n-FinFET was analyzed and discussed. Increased temperature led to degraded performance of some basic parameters such as subthreshold swing, transconductance, on-current, and leakage current. These results might be useful for further development of devises to strongly down-scale the manufacturing process.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.112.1-112.1
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• 2011

The back contact solar cell (BCSC) has several advantages compared to the conventional solar cell since it can reduce grid shadowing loss and contact resistance between the electrode and the silicon substrate. This paper presents the effect of the surface texturing of the silicon BCSC by varying the texturing depth or the texturing gap in the commercially available simulation software, ATHENA and ATLAS of the company SILVACO. The texturing depth was varied from $5{\mu}m$ to $150{\mu}m$ and the texturing gap was varied from $1{\mu}m$ to $100{\mu}m$ in the simulation. The resulting efficiency of the silicon BCSC was evaluated depending on the texturing condition. The quantum efficiency and the I-V curve of the designed silicon BCSC was also obtained for the analysis since they are closely related with the solar cell efficiency. Other parameters of the simulated silicon BCSC are as follows. The substrate was an n-type silicon, which was doped with phosphorous at $6{\times}10^{15}cm^{-3}$, and its thickness was $180{\mu}m$, a typical thickness of commercial solar cell substrate thickness. The back surface field (BSF) was $1{\times}10^{20}\;cm^{-3}$ and the doping concentration of a boron doped emitter was $8.5{\times}10^{19}\;cm^{-3}$. The pitch of the silicon BCSC was $1250{\mu}m$ and the anti-reflection coating (ARC) SiN thickness was $0.079{\mu}m$. It was assumed that the texturing was anisotropic etching of crystalline silicon, resulting in texturing angle of 54.7 degrees. The best efficiency was 25.6264% when texturing depth was $50{\mu}m$ with zero texturing gap in case of low texturing depth (< $100{\mu}m$).