• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.92-92
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• 2009

본 논문에서는 strained Silicon-on-Insulator (sSOI) 기판에 제작된 triple-gate MOSFETs 의 이동도와 단채널 효과에 대하여 분석 하였다. Strained 실리콘에 제작된 소자는 전류의 방향이 <110> 밤항일 경우 전자의 이동도는 증가하나 정공의 이동도는 오히려 감소하는 문제점이 있다. 이를 극복하기 위하여 소자에서 전류의 방향이 <110>방향에서 45 도 회전된 <100> 방향으로 흐르게 제작하였다. Strain이 가해지지 않은 기판에 제작된 동일한 구조의 소자와 비교하여 sSOI 에 제작된 소자에서 전자의 이동도는 약 40% 정공의 이동도는 약 50% 증가하였다. 채널 길이가 100 nm 내외로 감소함에 따라 나타나는 drain induced barrier lowering (DIBL) 현상, subthreshold slope (SS)의 증가 현상에서 sSOI에 제작된 소자가 상대적으로 우수한 특성을 보였으며 off-current leakage ($I_{off}$) 특성도 sSOI기판이 더 우수한 특성을 보였다.

• Electrical & Electronic Materials
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• v.7 no.4
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• pp.331-340
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• 1994

Polysilicon on insulator has been recrystallized by zone melting recrystallization method with graphite strip heaters. Experiments are performed with non-seed SOI structures. When the capping layer thickness of Si$\_$3/N$\_$4//SiO$\_$2/ is 2.0.mu.m, grain boundaries are about 120.mu.m spacing and protrusions reduced. After the seed SOI films are annealed at 1100.deg. C in NH$\_$3/ ambient for 3 hours, the recrystallized silicon surface has convex shape. After ZMR process, the tensile stress is 2.49*10$\^$9/dyn/cm$\^$2/ and 3.74*10$\^$9/dyn/cm$\^$2/ in the seed edge and seed center regions. The phenomenon of convex shape and tensile stress difference are completely eliminated by using the PSG/SiO$\_$2/ capping layer. The characterization of SOI films are showed that the SOI films are improved in wetting properties. N channel SOI MOSFET has been fabricated to investigate the electrical characteristics of the recrystallized SOI films. In the 0.7.mu.m thickness SOI MOSFET, kink effects due to the floating substrate occur and the electron mobility was calculated from the measured g$\_$m/ characteristics, which is about 589cm$\^$2//V.s. The recrystallized SOI films are shown to be a good single crystal silicon.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.7-8
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• 2006

The effects of heat treatment on the electrical properties of SGOI were examined. We proposed the optimized heat treatments for improving the interfacial electrical properties in SGOI-MOSFET. By applying the additional pre-RTA(rapid thermal annealing) before gate oxidation and post-RTA after dopant activation, the driving current, the transconductance, and the leakage current were improved significantly.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.10-10
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• 2010

ESD (Electrostatic Discharge) phenomenon occurs in everywhere and especially it damages to semiconductor devices. For ESD protection, there are some devices such as diode, GGNMOS (Gate-Grounded NMOS), SCR (Silicon-Controlled Rectifier), etc. Among them, diode and GGNMOS are usually chosen because of their small size, even though SCR has greater current capability than GGNMOS. In this paper, a novel SCR is proposed on the SOI (Silicon-On-Insulator) structure which has $1{\mu}m$ film thickness. In order to design and confirm the proposed SCR, TSUPREM4 and MEDICI simulators are used, respectively. According to the simulation result, although the proposed SCR has more compact size, it's electrical performance is better than electrical characteristics of conventional GGNMOS.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1085-1088
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• 2003

In this work, we fabricated a gas-sensing device based on porous silicon(PS), and its I-V and C-V properties were investigated for sensing alcohol vapor. The structure of the sensor consists of thin Au/Oxidized porous silicon/porous silicon/Silicon/Al, where the silicon substrate is etched anisotropically to be prepared into a membrane shape. As the result, I-V curves showed typical tunneling property, and C-V curves were shaped like those of a MIS (metal-insulator- semiconductor) capacitor, where the capacitance in accumulation was increased with alcohol vapor concentration.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.145-146
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• 2005

This study performs a simulation for an accumulation mechanism of contaminants, which were produced in an industrial belt of inland, on the surface of insulators. From the simulation, silicon insulators presented higher accumulation than that of EPDM(Ethylene Propylene Diene Terpolymer : EPDM) insulators on the same distance in the case of the Virgin polymer insulator, and this result presented the same result in the insulator applied in actual fields. In the case of the accumulation test for the Virgin insulator and insulators used in actual fields, it is evident that the Virgin insulator presented more accumulation than that of the insulator used in actual fields. The results can be caused by the generation of LMW (Low Molecular Weight) on the external material of polymer insulators, and the level of the accumulation can be changed according to the degree of the continuous generation of LMW.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.40 no.2
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• pp.111-117
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• 2016

The primary concern of this research is to examine the phonon mean free path (MFP) spectrum contribution to heat conduction. The size effect of materials is determined by phonon MFP, and the size effect appears when the phonon MFP is similar to or less than the characteristic length of materials. Therefore, knowledge of the phonon MFP is essential to increase or decrease the heat conduction of a material for engineering applications, such as micro/nanosystems. In this study, frequency dependence of the phonon transport is considered using the Boltzmann transport equation based on a full phonon dispersion model. Additionally, the phonon MFP spectrums of in-plane and out-of-plane heat transport are investigated by varying the film thickness of the silicon layer from 41 nm to 177 nm. This will increase the understanding of anisotropic heat conduction in a SOI (Silicon-on-Insulator) transistor.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.11
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• pp.698-703
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• 2015

In this study, we fabricated the dual gate (DG) ion-sensitive field-effect-transistor (ISFET) with flexible polyimide (PI) extended gate (EG). The DG ISFETs significantly enhanced the sensitivity of pH in electrolytes from 60 mV/pH to 1152.17 mV/pH and effectively improved the drift and hysteresis phenomenon. This is attributed to the capacitive coupling effect between top gate and bottom gate insulators of the channel in silicon-on-transistor (SOI) metal-oxide-semiconductor (MOS) FETs. Accordingly, it is expected that the PI-EG based DG-ISFETs is promising technology for high-performance flexible biosensor applications.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.6
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• pp.312-315
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• 2004

The monolayer of oxygen atoms sandwiched between the adjacent nanocrystalline silicon layers was formed by ultra high vacuum-chemical vapor deposition (UHV-CVD). This multilayer Si-O structure forms a new type of superlattice, semiconductor-atomic superlattice (SAS). According to the experimental results, high-resolution cross-sectional transmission electron microscopy (HRTEM) shows epitaxial system. Also, the current-voltage (Ⅰ-Ⅴ) measurement results show the stable and good insulating behavior with high breakdown voltage. It is apparent that the system may form an epitaxially grown insulating layer as possible replacement of silicon-on-insulator (SOI), a scheme investigated as future generation of high efficient and high density CMOS on SOI.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.546-548
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• 1987

We have studied 1iquid phase regrowth of phosphorus ion implanted silicon films on insulator (SOI) by rapid thermal annealing (RTA) method. Many twin boundaries were observed on the regrown silicon layer and mobility of the layer was increased from $14\;cm^2/v.sec$ to $38\;cm^2/v.sec$ after annealing at $1150^{\circ}C$ for 15 sec.