• Journal of the Korean institute of surface engineering
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• v.29 no.6
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• pp.773-780
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• 1996

Silicon oxide films were prepared by using five kinds of organosilicon compound as gas sources without oxygen by rf plasma-enhanced CVD (PECVD). UV light was irradiated on a substrate vertically during deposition to enhance film oxidation and ablation of carbon contamination in a deposited films. Films prepared with UV irradiation contained less carbon than those prepared without UV irradiation. The oxidation of the films was improved by UN irradiation. The effect of UV irradiation was, however, not observed when the films were prepared with tetramethy lsilane (TMS) which contained no oxygen atom. Dissociated oxygen atoms from an organosilicon compound were excited in the plasma with UV irradiation around the substrate surface and affected the enhancement of film oxidation and ablation of carbon in the films.

• Bulletin of the Korean Chemical Society
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• v.33 no.1
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• pp.83-89
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• 2012

Due to the potential importance and usefulness, usage of highly ordered nanoporous anodized aluminum oxide can be broadened in industry, when highly ordered anodized aluminum oxide can be placed on a substrate with controlled thickness. Here we report a facile route to highly ordered nanoporous alumina with the thickness of hundreds-of-nanometer on a silicon wafer substrate. Hexagonally or tetragonally ordered nanoporous alumina could be prepared by way of thermal imprinting, dry etching, and anodization. Adoption of reusable polymer soft molds enabled the control of the thickness of the highly ordered porous alumina. It also increased reproducibility of imprinting process and reduced the expense for mold production and pattern generation. As nanoporous alumina templates are mechanically and thermally stable, we expect that the simple and costeffective fabrication through our method would be highly applicable in electronics industry.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.3_1spc
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• pp.544-550
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• 2013

A grooved surface with anisotropic wettability was fabricated on a silicon substrate using photolithography, reactive ion etching, and a KOH etching process. The contact angles (CAs) of water droplets were measured and compared with the theoretical values in the Cassie state and Wenzel state. The experimental results showed that the contact area between a water droplet and a solid surface was important to determine the wettability of the water. The specimens with native oxide layers presented CAs ranging from $71.6^{\circ}$ to $86.4^{\circ}$. The droplets on the specimens with a native oxide layer could be in the Cassie state because they had relatively smooth surfaces. However, the CAs of the specimens with thick oxide layers ranged from $33.4^{\circ}$ to $59.1^{\circ}$. This indicated that the surface roughness for a specimen with a relatively thick oxide layer was higher, and the water droplet was in the Wenzel state. From the CA measurement results, it was observed that the wetting on the grooved surface was anisotropic for all of the specimens.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.34-39
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• 2014

This paper discusses the 3-level charge pumping (CP) method in planar-type Silicon-Oxide-High-k-Oxide-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason of the degradation of data retention properties. In the CP technique, pulses are applied to the gate of the MOSFET which alternately fill the traps with electrons and holes, thereby causing a recombination current Icp to flow in the substrate. The 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1065-1068
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• 2003

For the first time, high quality ultra-thin strained Si/SiGe on Insulator (SGOI) substrate with total SGOI thickness( $T_{Si}$ + $T_{SiGe}$) of 13 nm is developed to combine the device benefits of strained silicon and SOI. In the case of 6- 10 nm-thick top silicon, 100-110 % $I_{d,sat}$ and electron mobility increase are shown in long channel nFET devices. However, 20-30% reduction of $I_{d,sat}$ and electron mobility are observed with 3 nm top silicon for the same long channel device. These results clearly show that the FETs operates with higher performance due to the strain enhancement from the insertion of SiGe layer between the top silicon layer and the buried oxide(BOX) layer. The performance degradation of the extremely thin( 3 nm ) top Si device can be attributed to the scattering of the majority carriers at the interfaces.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.995-997
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• 2005

A plastic substrate for flexible display is developed. The gas barrier and optical properties of the substrate is improved through depositing silicon oxide/nitride layer and coating polymer layer on plastic film by sputtering process and wet coating process. Roll to roll processes will guarantee the productivity in the whole production process of the plastic substrate.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2005.11a
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• pp.160-163
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• 2005

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.328-331
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• 1988

Sealed Interface Local Oxidation (SILO) technology has been investigated using a nitride/oxide/nitride three-layered sandwich structure. P-type silicon substrate was either nitrided by rapid thermal processing, or silicon nitride was deposited by LPCVD method. A three-layered sandwich structure was patterned either by reactive ion etch (RIE) mode or by plasma mode. Sacrificial oxidation conditions were also varied. Physical characterization such as cross-section analysis of field oxide, and electrical characterization such as gate oxide integrity, junction leakage and transistor behavior were carried out. It was found that bird's beak was nearly zero or below 0.1um, and the junction leakages in plasma mode were low compared to devices of the same geometry patterned in RIE mode, and gate oxide integrity and transistor behavior were comparable. Conclusively, SILO process is compatible with conventional local oxidation process.

• ETRI Journal
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• v.15 no.2
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• pp.11-25
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• 1993

Interface trap densities at gate oxide/silicon substrate ($SiO_2/Si$) interfaces of metal oxide semiconductor field-effect transistors (MOSFETs) were determined from the substrate bias dependence of the subthreshold slope measurement. This method enables the characterization of interface traps residing in the energy level between the midgap and that corresponding to the strong inversion of small size MOSFET. In consequence of the high accuracy of this method, the energy dependence of the interface trap density can be accurately determined. The application of this technique to a MOSFET showed good agreement with the result obtained through the high-frequency/quasi-static capacitance-voltage (C-V) technique for a MOS capacitor. Furthermore, the effective substrate dopant concentration obtained through this technique also showed good agreement with the result obtained through the body effect measurement.

• Electronics and Telecommunications Trends
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• v.5 no.1
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• pp.55-70
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• 1990

SIMOX SOI is known to be one of the most useful technologies for fabrications of new generation ULSI devices. This paper describes the current status of SIMOX SOI technology for ULSI applications. The SIMOX wafer is vertically composed of buried oxide layer and silicon epitaxial layer on top of the silicon substrate. The buried oxide layer is used for the vertical isolation of devices The oxide layer is formed by high energy ion implantation of high dose oxygen into the silicon wafer, followed by high temperature annealing. SIMOX-based CMOS fabrication is transparent to the conventional IC processing steps without well formation. Furthermore, thin film CMOX/SIMOX can overcome the technological limitations which encountered in submicron bulk-based CMOS devices, i.e., soft-error rate, subthreshold slope, threshold voltage roll-off, and hot electron degradation can be improved. SIMOX-based bipolar devices are expected to have high density which comparable to the CMOX circuits. Radiation hardness properties of SIMOX SOI extend its application fields to space and military devices, since military ICs should be operational in radiation-hardened and harsh environments. The cost of SIMOX wafer preparation is high at present, but it is expected to reduce as volume increases. Recent studies about SIMOX SOI technology have demonstrated that the performance of the SIMOX-based submicron devices is superior to the circuits using the bulk silicon.