• Korean Journal of Crystallography
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• v.12 no.3
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• pp.166-170
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• 2001

Dopants implanted in silicon substrate affect the reaction between cobalt and silicon substrate. Phosphorous, unlike boron and arsenic, suppressing the reaction between cobalt and silicon induces CoSi formation during a low temperature thermal treatment instead of CoSi₂formation. The CoSi layer should move to the silicon substrate to fill the vacant volume that is generated in the silicon substrate due to the silicon out-diffusion into the cobalt/CoSi interface. The movement of CoSi at gate sidewall spacer region is suppressed by a cohesion between gate oxide and CoSi layers, resulting in a void formation at the gate sidewall spacer edge.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.199-199
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• 2008

이 실험은 NVM의 Oxide, Nitride, Oxide nitride층별 blocking, trapping and tunneling 속성에 대해서 밝히고자 한다. gate 전극은 값싸고 전도도가 좋은 알루미늄을 사용한다. 유리기판위에 Silicon nitride층을 20nm로 코팅하고 Silicon dioxide층을 10nm로 코팅한다. 그리고 amorphous Silicon material이 증착된다. Poly Silicon은 Solid Phase Crystallization 방법을 사용하였다. 마지막 공정으로 p-doping은 ion shower에 의한 방법으로 drain과 source 전극을 생성하였다. gate가 biasing 될 때, p-channel은 source와 drain 사이에서 형성된다. Oxide Nitride Oxide nitride (ONO) 층은 각각 12.5nm/20nm/2.3nm의 두께로 만들었다. 전하는 Program process 중에 poly Silicon층에서 Silicon Oxide nitride tunneling층을 통하여 움직이게 된다. 그리고 전하들은 Silicon Nitride층에 머무르게 된다. 그 전하들은 erasing process 중에 trapping 층에서 poly Silicon 층으로 되돌아 간다. Silicon Oxide blocking층은 trapping층으로 전하가 나가는 것을 피하기 위하여 더해진다. 이 논문에서 Programming process와 erasing process의 Id-Vg 특성곡선을 설명한다. Programming process에 positive voltage를 또는 erasing process에 negative voltage를 적용할 때, Id-Vg 특성 곡선은 왼쪽 또는 오른쪽으로 이동한다. 이 실험이 보여준 결과값에 의해서 10년 이상의 저장능력이 있는 메모리를 만들 수 있다. 그러므로, NVM의 중요한 두 가지 성질은 유지성과 내구성이다.

• Tribology and Lubricants
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• v.18 no.4
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• pp.260-266
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• 2002

In this study, the effects of oxide layer farmed on the wear tracks of TiN coated silicon wafer on friction and wear characteristics were investigated. Silicon wafer was used for the substrate of coated disk specimens, which were prepared by depositing TiN coating with 1 ${\mu}{\textrm}{m}$ in coating thickness. AISI 52100 steel ball was used fur the counterpart. The tests were performed both in air for forming oxide layer on the wear track and in nitrogen to avoid oxidation. This paper reports characterization of the oxide layer effects on friction and wear characteristics using X-ray diffraction(XRD), Auger electron spectroscopy(AES), scanning electron microscopy (SEM) and multi-mode atomic force microscope(AFM).

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.10b
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• pp.167-168
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• 2002

In this study, the effects of oxide layer formed on the wear tracks of TiN coated silicon wafer on friction characteristics were investigated. Silicon wafer was used for the substrate of coated disk specimens, which were prepared by depositing TiN coating with $1\;{\mu}m$ in coating thickness. AISI 52100 steel balls were used for the counterpart. The tests were performed both in air for forming oxide layer on the wear track and in nitrogen to avoid oxidation. This paper reports characterization of the oxide layer effects on friction characteristics using X-ray diffraction (XRD). scanning electron microscopy (SEM) and friction force microscope (FFM).

• Korean Journal of Materials Research
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• v.18 no.10
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• pp.521-528
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• 2008

We present the structural, optical, and electrical properties of amorphous silicon suboxide (a-$SiO_x$) films grown on indium tin oxide glass substrates with a radio frequency magnetron technique from a polycrystalline silicon oxide target using ambient Ar. For different substrate-target distances (d = 8 cm and 10 cm), the deposition temperature effects were systematically studied. For d = 8cm, oxygen content in a-$SiO_x$ decreased with dissociation of oxygen onto the silicon oxide matrix; temperature increased due to enlargement of kinetic energy. For d = 10 cm, however, the oxygen content had a minimum between $150^{\circ}\;and\;200^{\circ}$. Using simple optical measurements, we can predict a preferred orientation of liquid crystal molecules on a-$SiO_x$ thin film. At higher oxygen content (x > 1.6), liquid crystal molecules on an inorganic liquid crystal alignment layer of a-$SiO_x$ showed homogeneous alignment; however, in the lower case (x < 1.6), liquid crystals showed homeotropic alignment.

• Journal of the Korean institute of surface engineering
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• v.29 no.5
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• pp.577-584
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• 1996

Silicon oxide films with high hardness and water repellency were prepared by microwave plasma-enhanced CVD using four kind of organosilicon compound-fluoro-alkyl silane mixtures as source gases. An argon gas was used as a carrier gas for fluoro-alkyl silane. The substrate temperatures during deposition were controlled by resistant heating at a constant value between 50 and $300^{\circ}C$. The hardness of the films increased, but the deposition rate and the contact angle for a water drop decreased with increasing substrate temperature. The number of methoxy groups also affected the water repellency and hardness. The deposited films became more inorganic with increasing substrate temperature because of the thermal dissociation of reactants.

• Korean Journal of Materials Research
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• v.20 no.8
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• pp.423-428
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• 2010

This study shows the effects of deionized (DI) rinse and oxide HF wet etch processes on silicon substrate during a photolithography process. We found a fail at the wafer center after DI rinse step, called Si pits, during the fabrication of a complementary metal-oxide-semiconductor (CMOS) device. We tried to find out the mechanism of the Si pits by using the silicon wafer on CMOS fabrication and analyzing the effects of the friction charge induced by the DI rinsing. The key parameters of this experiment were revolution per minute (rpm) and time. An incubation time of above 10 sec was observed for the formation of Si pits and the rinsing time was more effective than rpm on the formation of the Si pits. The formation mechanism of the Si pits and optimized rinsing process parameters were investigated by measuring the charging level using a plasma density monitor. The DI rinse could affect the oxide substrate by a friction charging phenomenon on the photolithography process. Si pits were found to be formed on the micro structural defective site on the Si substrate under acceleration by developed and accumulated charges during DI rinsing. The optimum process conditions of DI rinse time and rpm could be established through a systematic study of various rinsing conditions.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.52.1-52.1
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• 2009

Cupric oxide (CuO) is a p-type semiconductor with band gap of ~1.7 eV and reported to be suitable for catalysis, lithium-copper oxide electrochemical cells, and gas sensors applications. The nanoparticles, plates and nanowires of CuO were found sensing to NO2, H2S and CO. In this work, we report about the comparison about hydrogen sensing of nano thin film and nanowires structured CuO deposited on single-walled carbon nanotubes (SWNTs). The thin film and nanowires are synthesized by deposition of Cu on different substrate followed by oxidation process. Nano thin films of CuO are deposited on thermally oxidized silicon substrate, whereas nanowires are synthesized by using a porous thin film of SWNTs as substrate. The hydrogen sensing properties of synthesized materials are investigated. The results showed that nanowires cupric oxide deposited on SWNTs showed higher sensitivity to hydrogen than those of nano thin film CuO did.

• Transactions on Electrical and Electronic Materials
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• v.14 no.5
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• pp.250-253
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• 2013

In this paper, we fabricated 3D pillar type silicon-oxide-nitride-oxide-silicon (SONOS) devices for high density flash applications. To solve the limitation between erase speed and data retention of the conventional SONOS devices, bandgap-engineered (BE) tunneling oxide of oxide-nitride-oxide configuration is integrated with the 3D structure. In addition, the tunneling oxide is modulated by another method of $N_2$ ion implantation ($N_2$ I/I). The measured data shows that the BE-SONOS device has better electrical characteristics, such as a lower threshold voltage ($V_{\tau}$) of 0.13 V, and a higher $g_{m.max}$ of 18.6 ${\mu}A/V$ and mobility of 27.02 $cm^2/Vs$ than the conventional and $N_2$ I/I SONOS devices. Memory characteristics show that the modulated tunneling oxide devices have fast erase speed. Among the devices, the BE-SONOS device has faster program/erase (P/E) speed, and more stable endurance characteristics, than conventional and $N_2$ I/I devices. From the flicker noise analysis, however, the BE-SONOS device seems to have more interface traps between the tunneling oxide and silicon substrate, which should be considered in designing the process conditions. Finally, 3D structures, such as the pillar type BE-SONOS device, are more suitable for next generation memory devices than other modulated tunneling oxide devices.

• Korean Journal of Materials Research
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• v.12 no.4
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• pp.240-247
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• 2002

Tin oxide thin films doped with silicon as anodes for lithium secondary battery were fabricated by R.F. magnetron sputtering technique. The electrochemical results showed that the irreversible capacity was reduced during the first discharge/charge cycle, because the audition of silicon decreased the oxidic state of Tin. Capacity was increased with the increase of substrate temperature, however decreased with the increase of RTA temperatures. The reversible capacity of thin films fabricated under the substrate temperature of $300^{\circ}C$ and the Ar:$O_2$ratio of 7:3 was 700mA/g.