• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.30 no.6
• /
• pp.401-405
• /
• 2017

Because silicon thin film solar cells have a high absorption coefficient in visible light, they can absorb 90% of the solar spectrum in a $1-{\mu}m$-thick layer. Silicon thin film solar cells also have high transparency and are lightweight. Therefore, they can be used for building integrated photovoltaic (BIPV) systems. However, the contact electrode needs to be replaced for fabricating silicon thin film solar cells in BIPV systems, because most of the silicon thin film solar cells use metal electrodes that have a high reflectivity and low transmittance. In this study, we replace the conventional aluminum top electrode with a transparent aluminum-doped zinc oxide (AZO) electrode, the band level of which matches well with that of the intrinsic layer of the silicon thin film solar cell and has high transmittance. We show that the AZO effectively replaces the top metal electrode and the bottom fluorine-doped tin oxide (FTO) substrate without a noticeable degradation of the photovoltaic characteristics.

• Journal of the Korean Ceramic Society
• /
• v.20 no.4
• /
• pp.305-314
• /
• 1983

In order to enhance the rate of th nitridation and to give the high density of reaction-bonded silicon nitride MgO powder as nitriding aid were added to silicon powders and the mixture was pressed isostatically into compacts which were nitrided in the furnace of 1, 35$0^{\circ}C$ where 95% $N_2$-5% $H_2$ gases were flowing. As the other nitriding aid $Mg(NO_3)_2 6H_2O$ was selected, A slip made of magnesium nitrate solution and fine silicon particles was spray-dried and then decomposed at 30$0^{\circ}C$. Magnesium oxide-coated silicon powders were formed into compacts prior to the nitridation on the same condition as the former. Magnesium nitrate (MgO, produced from the decomposition of magnesium nitrate) was more effective for the formation of the $\beta$-phase in the initial stage of the nitridation probably due to the easy formation of $MgO-SiO_2$-metal oxide eutectic melt. It has been confirmed that forsterite was formed as a result of the reaction between MgO and $SiO_2$ film of silicon surface. It was considered that MgO produced from magnesium nitrate may be finer more reactive and more uniformly distributed on the surface of silicon particles than original MgO. The higher the forming pressure was the more the $\beta$-phase was formed.

• Proceedings of the KIEE Conference
• /
• 1996.07c
• /
• pp.1988-1990
• /
• 1996

In this work, we have grown or evaporated thermal oxide and E-beam oxide on the (100) oriented n-type silicon wafers, respectively and they were directly bonded with another silicon wafer after hydrophilization using solutions of three types of $HNO_3$, $H_{2}SO_{4}$ and $NH_{4}OH$. Changes of average surface roughness after hydrophilizations of the single crystalline silicon wafer, thermal oxide and E-beam evaporated silicon oxide were studied using atomic force microscope. Bonding interfaces of the bonded pairs were inspected using scanning electron microscope. Void and non-contact area of the bonded pairs were also inspected using infrared transmission microscope.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.08a
• /
• pp.229-229
• /
• 2011

부유 게이트 Floating gate (FG) 플래시 메모리 소자의 단점을 개선하기 위해 전하 포획 층에 전하를 저장하는 전하 포획 플래시 메모리 Charge trap flash (CTF)소자에 대한 연구가 활발히 진행되고 있다. CTF소자는 FG플래시 메모리 소자에 비해 비례축소가 용이하고 긴 retention time을 가지며, 낮은 구동 전압을 사용하는 장점을 가지고 있다. CTF 소자에서 비례축소에 따라 단채널 효과와 펀치-쓰루 현상이 증가하는 문제점이 있다.본 연구에서는 CTF 단채널 효과와 펀치-쓰루 현상을 감소시키기 위한 방법으로 silicon-on-insulator (SOI) 기판을 사용하였으며 SOI기판에서 절연층의 깊이에 따른 전기적 특성을 고찰하였다. silicon-oxide-nitride-oxide-silicon(SONOS) 구조를 가진 CTF 메모리 소자를 사용하여 절연층의 깊이 변화에 따른 subthreshold swing특성, 쓰기-지우기 동작 특성을 TCAD 시뮬레이션 툴인 Sentaurus를 사용하여 조사하였다. 소스와 드레인의 junction depth는 20 nm 사용하였고, 절연층의 깊이는 5 nm~25 nm까지 변화하면서 절연층의 깊이가 20 nm이하인 fully depletion 소자에 비해, 절연층의 깊이가 25 nm인 소자는 partially depletion으로 인해서 드레인 전류 레벨이 낮아지고 subthreshold swing값이 증가하는 현상이 나타났다. 절연층의 깊이가 너무 얕을 경우, 채널 형성의 어려움으로 인해 subthreshold swing과 드레인 전류 레벨의 전기적성질이 SOI기판을 사용하지 않았을 경우보다 떨어지는 경향을 보였다. 절연층의 깊이가 17.5 nm인 경우, CTF소자의 subthreshold swing과 드레인 전류 레벨이 가장 좋은 특성을 보였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.29 no.6
• /
• pp.321-326
• /
• 2016

Minimizing the carrier recombination and electrical loss through surface passivation is required for high efficiency c-Si solar cell. Usually, $SiN_X$, $SiO_X$, $SiON_X$ and $AlO_X$ layers are used as passivation layer in solar cell application. Silicon oxide layer is one of the good passivation layer in Si based solar cell application. It has good selective carrier, low interface state density, good thermal stability and tunneling effect. Recently tunneling based passivation layer is used for high efficiency Si solar cell such as HIT, TOPCon and TRIEX structure. In this paper, we focused on silicon oxide grown by various the method (thermal, wet-chemical, plasma) and passivation effect in c-Si solar cell.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2016.02a
• /
• pp.406-406
• /
• 2016

To get high efficiency n-type crystalline silicon solar cells, passivation is one of the key factor. Tunnel oxide (SiO2) reduce surface recombination as a passivation layer and it does not constrict the majority carrier flow. In this work, the passivation quality enhanced by different chemical solution such as HNO3, H2SO4:H2O2 and DI-water to make thin tunnel oxide layer on n-type crystalline silicon wafer and changes of characteristics by subsequent annealing process and firing process after phosphorus doped amorphous silicon (a-Si:H) deposition. The tunneling of carrier through oxide layer is checked through I-V measurement when the voltage is from -1 V to 1 V and interface state density also be calculated about $1{\times}1012cm-2eV-1$ using MIS (Metal-Insulator-Semiconductor) structure . Tunnel oxide produced by 68 wt% HNO3 for 5 min on $100^{\circ}C$, H2SO4:H2O2 for 5 min on $100^{\circ}C$ and DI-water for 60 min on $95^{\circ}C$. The oxide layer is measured thickness about 1.4~2.2 nm by spectral ellipsometry (SE) and properties as passivation layer by QSSPC (Quasi-Steady-state Photo Conductance). Tunnel oxide layer is capped with phosphorus doped amorphous silicon on both sides and additional annealing process improve lifetime from $3.25{\mu}s$ to $397{\mu}s$ and implied Voc from 544 mV to 690 mV after P-doped a-Si deposition, respectively. It will be expected that amorphous silicon is changed to poly silicon phase. Furthermore, lifetime and implied Voc were recovered by forming gas annealing (FGA) after firing process from $192{\mu}s$ to $786{\mu}s$. It is shown that the tunnel oxide layer is thermally stable.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07a
• /
• pp.354-357
• /
• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• Journal of the Society of Disaster Information
• /
• v.18 no.3
• /
• pp.478-486
• /
• 2022

Purpose: Although the working environment is measured at the construction site, only a few noise and vibration that are typically exposed for each process are performed without measuring the working environment by segmenting the exposed harmful factors. Therefore, it is intended to find the harmfulness of silicon oxide dust, which is most exposed at construction sites, and the complementary points of improvement measures currently being implemented at construction sites. Method: The status was analyzed using the actual condition survey report issued by the Korea Occupational Health Corporation and the Korea Occupational Health Association and data from the work environment measurement institution, and compared and analyzed with the rules on work environment measurement of the Occupational Safety and Health Act. Result: The harmfulness of silicon oxide dust was identified and improvement measures were derived. Conclusion: It is expected that occupational diseases against silicon dust can be reduced if the harmfulness of silicon oxide dust at construction sites is derived and improvement measures are actively applied at the site.

• Proceedings of the KIEE Conference
• /
• 1992.07b
• /
• pp.820-824
• /
• 1992

An accurate method for extracting both Si film doping concentration and front or back silicon-to-oxide fixed charge density of fully depleted SOI devices is proposed. The method utilizes the current-to-voltage and capacitance-to-voltage characteristics of both SOI NMOSFET and PMOSFET which have the same doping concentration. The Si film doping concentration and the front or back silicon-to-oxide fixed charge density are extracted by mainpulating the respective threshold voltages of the SOI NMOSFET and PMOSFET according to the back surface condition (accumulation or inversion) and the capacitance-to-voltage characteristics of the SOI PMOSFET. Device simulations show that the proposed method has less than 10% errors for wide variations of the film doping concentration and the front or the back silicon-to-oxide fixed charge density.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.11a
• /
• pp.119-119
• /
• 2008

The electrical characteristics of Metal-Ferroelectric-Nitride-Oxide-Silicon (MFNOS) structure is studied and compared to the conventional Silicon-Oixde-Nitride-Oxide-Silicon (SONOS) capacitor. The ferroelectric blocking layer is SrBiNbO (SBN with Sr/Bi ratio 1-x/2+x) with the thickness of 200 nm and is fabricated by the RF sputter. The memory windows of MFNOS and SONOS capacitors with sweep voltage from +10 V to -10 V are 6.9 V and 5.9 V, respectively. The effect of ferroelectric blocking layer and charge trapping on the memory window was discussed. The retention of MFNOS capacitor also shows the 10-years and longer retention time than that of the SONOS capacitor. The better retention properties of the MFNOS capacitor may be attributed to the charge holding effect by the polarization of ferroelectric layer.