• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.90-99
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• 1984

A onetimensional distribution of the temperature and the heat source in the SOI (silicon-on-insulator) multi-layer structure illuminated by tungsten lamps from both sides was obtained by solving the heat equation in steady state on a finite difference grid using successive over-relaxation method. The heat source distribution was obtained by considering such features as spectral components of the light source, multiple reflection at the internal interfaces, temperature and frequency dependence of the light absorption coefficient, etc. The front and back surface temperatures, which are boundary conditions for the heat equation, were derived from a requirement that they satisfy the radiation conditions. The radiation flux as well as the conduction flux was considered in modelling the thermal behaviour at the internal interfaces. Since the temperature and the heat source profiles are strongly dependent upon each other, the calculation of each profile was iterated using the updated profile of the other until they are consistent with each other. The experimental temperature at the front surface of the wafer as measured by Pyrometer was about 1200$^{\circ}$K, while the simulated temperature was 1120$^{\circ}$K.

• Journal of the Korean Vacuum Society
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• v.10 no.3
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• pp.361-367
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• 2001

Recently, Chemical Mechanical Polishing(CMP) has become a leading planarization technique as a method for silicon wafer planarization that can meet the more stringent lithographic requirement of planarity for the future submicron device manufacturing. The SOI(Silicon On Insulator) wafer has received considerable attention as bulk-alternative wafer to improve the performance of semiconductor devices. In this paper, the objective of study is to investigate Material Removal Rate(MRR) and surface micro-roughness effects of slurry and pad in the CMP process. When particle size of slurry is increased, Material Removal rate increase. Surface micro-roughness is greater influenced by pad than by particle size of slurry. As a result of AM measurement, surface micro-roughness was improved from 27 $\AA$ Rms to 0.64 $\AA$Rms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.51-56
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• 2004

We propose and fabricate an 1${\times}$2 asymmetric optical switch by TOE using SOI wafer based on silicon which has very large TOE figure and it is a good material for optical devices. SOI wafer consists of 3 layers; upper Si layer for device(waveguide;core, n=3.5), buried oxide layer for insulator(clad, n=1.5) and Si substrate layer. We designed 1${\times}$2 asymmetric y-branched single mode optical waveguide switch by BPM simulation and metal heater by heat transfer simulation. Fabricated switch shows about 3.5 watts of power consumption and over 20dB of crosstalk between output channels.

• Journal of Sensor Science and Technology
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• v.3 no.2
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• pp.74-80
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• 1994

Silicon direct bonding technology is very attractive for both silicon-on-insulator devices and sensor fabrication because of its thermal stress free structure and stability. The process of SDB includes hydration of silicon wafer and heat treatment in a wet oxidation furnace. After hydration process, hydroxyl groups of silicon wafer were analyzed by using Fourier transformation-infrared spectroscopy. In case of hydrophilic treatment using a ($H_{2}O_{2}\;:\;H_{2}SO_{4}$) solution, hydroxyl groups are observed in a broad band around the 3474 $cm^{-1}$ region. However, hydroxyl groups do not appear in case of diluted HF solution. The bonded wafer was etched by using tetramethylammonium hydroxide etchant. The surface of the self etch-stopped silicon dioxide is completely flat, so that it can be used as sensor applications such as pressure, flow and acceleration, etc..

• Transactions on Electrical and Electronic Materials
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• v.1 no.1
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• pp.6-11
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• 2000

The hydrogen plasma treatment of silicon wafers in the reactive ion-etching mode was studied for the application to silicon-on-insulator wafers which were prepared using the wafer bonding technique. The chemical reactions of hydrogen plasma with surface were used for both surface activation and removal of surface contaminants. As a result of exposure of silicon wafers to the plasma, an active oxide layer was found on the surface. This layer was rendered hydrophilic. The surface roughness and morphology were examined as functions of the plasma exposing time and power. In addition, the surface became smoother with the shorter plasma exposing time and power. The value of initial surface energy estimated by the crack propagation method was 506 mJ/㎡, which was up to about three times higher as compared to the case of conventional direct using the wet RCA cleaning method.

• Proceedings of the Korean Ceranic Society Conference
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• 2000.04a
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• pp.127.1-127.1
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• 2000

• Transactions of the Korean Society of Machine Tool Engineers
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• v.11 no.4
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• pp.12-18
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• 2002

Silicon on insulator(SOI) wafer is used in a variety of microsensor applications in which thermal deformations and other mechanical effects may dominate device Performance. One of major Problems associated with the manufacturing Processes of the microaccelerometer based on the tunneling current concept is thermal deformations and thermal stresses. This paper deals with finite element analysis(FEA) of residual thermal deformations causing popping up, which are induced in micrormaching processes of a microaccelerometer. The reason for this Popping up phenomenon in manufacturing processes of microaccelerometer may be the bending of the whole wafer or it may come from the way the underetching occurs. We want to seek after the real cause of this popping up phenomenon and diminish this by changing manufacturing processes of mic개accelerometer. In microaccelerometer manufacturing process, this paper intend to find thermal deformation change of the temperature distribution by tunnel gap and additional beams. The thermal behaviors analysis intend to use ANSYS V5.5.3.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2000.05a
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• pp.105-109
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• 2000

Micronization of sensor is a trend of the silicon sensor development with regard to a piezoresistive silicon pressure sensor the size of the pressure sensor diaphragm have become smaller year by year and a microaccelerometer with a size less than 200-300${\mu}m$ has been realized. In this paper we study some of the micromachining processes of SOI(silicon on insulator)for the microaccelerometer and their subsequent processes which might affect thermal loads. The finite element method(FEM) has been a standard numerical modeling technique extensively utilized in structural engineering discipline for design of SOI wafers. Successful thermal behaviors analysis and design of the SOI wafers based on the tunneling current concept using SOI wafer depend on the knowledge abut normal mechanical properties of the SCS(single crystal silicon)layer and their control through manufacturing process

• Current Optics and Photonics
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• v.3 no.6
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• pp.522-530
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• 2019

We present simulation methods to accurately determine the transmission efficiency and far-field patterns (FFPs) of a shallow-etched waveguide grating antenna (WGA) formed on a silicon-on-insulator wafer based on the finite-difference time-domain (FDTD) approach. The directionality and the FFP of a WGA with >1-mm in length can be obtained reliably by simulating a truncated WGA structure using a three-dimensional FDTD method and a full-scale WGA using a two-dimensional FDTD with the effective index method. The developed FDTD methods are applied to the simulation of an optical phased array (OPA) composed of a uniformly spaced WGA array, and the steering-angle dependent transmission efficiency and FFPs are obtained in OPA structures having up to 128-channel WGAs.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2504-2508
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• 1998

In this paper, we propose the new detecting method for three dimensional piezoresistive silicon accelerometer. Furthermore the accelerometer is formed to have endurance for high temperature by perfect isolation of the piezoresistors using Silicon On Insulator(SOI) wafer. Sensor size are optimized with analytical formulae and extended with FEM simulation for the more detailed results. The accelerometer was fabricated by bulk micromachining techonology. We measured the temperature characteristics and the output characteristics, and the both characteristics were compared with the simulated results