• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.830-833
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• 2003

This paper describes the fabrication and characteristics of 3C-SiCOI sotctures by SDB and etch-back technology for high-temperature MEMS applications. In this work, insulator layers were formed on a heteroepitaxial 3C-SiC film grown on a Si(001) wafer by thermal wet oxidation and PECVD process, successively. The pre-bonding of two polished PECVD oxide layers made the surface activation in HF and bonded under applied pressure. The wafer bonding characteristics were evaluated by the effect of HF concentration used in the surface treatment on the roughness of the oxide and pre-bonding strength. Hydrophilic character of the oxidized 3C-SiC film surface was investigated by ATR-FTIR. The strength of the bond was measured by tensile strengthmeter. The bonded interface was also analyzed by SEM. The properties of fabricated 3C-SiCOI structures using etch-back technology in TMAH solution were analyzed by XRD and SEM. These results indicate that the 3C-SiCOI structure will offers significant advantages in the high-temperature MEMS applications.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.7
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• pp.26-33
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• 1999

In order to examine the effect of beam location n the performance of bridge type piozoresistive silicon accelerometer, three sensors having different location of beams were simulated by FEN(finite element method) and fabricated by RIE(reactive ion etching) and KOH etching method using SDB(silicon direct bonding) wafer, Results of the FEM simulation present that the 1st resonace frequency and Z axis sensitivity of each sensor are identical but the 2nd, and the 3rd resonace frequency and X, Y axis sensitivity are different. Even though the 1st resonance frequency and Z axis sensitivity measured from fabricated sensors do not perfectly coincide with each other, all 3 type sensors present 180 ~ 220N/G of Z sensitivity at 5 V supply voltage and 1.3 ~ 1.7kHz of the 1st resonance frequency and about 2% of lateral sensitivity.

• The Korean Journal of Ceramics
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• v.7 no.1
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• pp.36-40
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• 2001

In order to fabricate uncooled IR sensors for pyroelectric applications, multilayered thin films of Pt/PbTiO$_3$/Pt/Ti/Si$_3$N$_4$/SiO$_2$/Si and thermally isolating membrane structures of square-shaped/cantilevers-shaped microstructures were prepared. Cavity was also fabricated via direct silicon wafer bonding and etching technique. Metallic Pt layer was deposited by ion beam sputtering while PbTiO$_3$ thin films were prepared by sol-gel technique. Micromachining technology was used to fabricate microstructured-membrane detectors. In order to avoid a difficulty of etching active layers, silicon-nitride membrane structure was fabricated through the direct bonding and etching of the silicon wafer. Although multilayered thin film deposition and device fabrications were processed independently, these could b integrated to make IR micro-sensor devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.6
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• pp.514-519
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• 2000

This paper describes on the temperature characteristics of a SDB(silicon-wafer direct bonding) SOI(silicon-on-insulator) Hall sensor. Using the buried oxide $SiO_2$as a dielectrical isolation layer a SDB SOI Hall sensor without pn junction has been fabricated on the Si/ $SiO_2$/Si structure. The Hall voltage and the sensitivity of the implemented SOI Hall sensor show good linearity with respect to the applied magnetic flux density and supplied current. In the temperature range of 25 to 30$0^{\circ}C$ the shifts of TCO(temperature coefficient of the offset voltage) and TCS(temperature coefficient of the product sensitivity) are less than $\pm$6.7$\times$10$_{-3}$ and $\pm$8.2$\times$10$_{-4}$$^{\circ}C$ respectively. These results indicate that the SDB SOI structure has potential for the development of a silicon Hall sensor with a high-sensitivity and high-temperature operation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.29-33
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• 2000

This paper describes on the temperature characteristics of a SDB(silicon-wafer direct bonding) SOI(silicon-on-insulator) Hall sensor. Using the buried oxide $SiO_2$ as a dielectrical isolation layer, a SDB SOI Hall sensor without pn junction isolation has been fabricated on the Si/$SiO_2$/Si structure. The Hall voltage and the sensitivity of the implemented SOI Hall sensor show good linearity with respect to the applied magnetic flux density and supplied current. In the temperature range of 25 to $300^{\circ}C$, the shifts of TCO(temperature coefficient of the offset voltage) and TCS(temperature coefficient of the product sensitivity) are less than ${\pm}6.7{\times}10^{-3}/^{\circ}C$ and ${\pm}8.2{\times}10^{-4}/^{\circ}C$, respectively. These results indicate that the SDB SOI structure has potential for the development of a silicon Hall sensor with a high-sensitivity and high-temperature operation.

• Journal of Sensor Science and Technology
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• v.1 no.2
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• pp.131-145
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• 1992

This paper has been described a process technology for the fabrication of Si-on-insulator(SOI) transducers and circuits. The technology utilizes Si-wafer direct bonding(SDB) and mechanical-chemical(M-C) local polishing to create a SOI structure with a high-qualify, uniformly thin layer of single-crystal Si. The electrical and piezoresistive properties of the resultant thin SOI films have been investigated by SOI MOSFET's and cantilever beams, and confirmed comparable to those of bulk Si. Two kinds of pressure transducers using a SOI structure have been proposed. The shifts in sensitivity and offset voltage of the implemented pressure transducers using interfacial $SiO_{2}$ films as the dielectrical isolation layer of piezoresistors were less than -0.2% and +0.15%, respectively, in the temperature range from $-20^{\circ}C$ to $+350^{\circ}C$. In the case of pressure transducers using interfacial $SiO_{2}$ films as an etch-stop layer during the fabrication of thin Si membranes, the pressure sensitivity variation can be controlled to within a standard deviation of ${\pm}2.3%$ from wafer to wafer. From these results, the developed SDB process and the resultant SOI films will offer significant advantages in the fabrication of integrated microtransducers and circuits.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.12
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• pp.977-982
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• 2000

Conventional transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area. These consequently have disadvantage for high speed switching performance. In this paper, a lateral structure transistor which has minimized parasitic capacitance by using SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics are designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance is proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed lateral structure transistor is certified through the V$\_$CE/-I$\_$C/ characteristics curve, h$\_$FE/-I$\_$C/ characteristics, and GP-plot. Cutoff Frequency is 13.7㎓.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.595-596
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• 2006

A novel Si via structure is suggested and fabricated for 3D MEMS package using the doped silicon as an interconnection material. Oxide isolations which define Si via are formed simultaneously when fabricating the MEMS structure by using DRIE and oxidation. Silicon Direct Bonding Multi-stacking process is used for stacked package, which consists of a substrate, MEMS structure layer and a cover layer. The bonded wafers are thinned by lapping and polishing. A via with the size of $20{\mu}m$ is fabricated and the electrical and mechanical characteristics of via are under testing.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.310-313
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• 2002

Structures obtained with a direct boning of two FZ silicon wafers joined in such a way that a smooth surface of one wafer was attached to the grooved surface of the other were studied. A square net of grooves was made with a conventional photo lithography process. After high temperature annealing the appearance of voids and the rearrangement of structural defects were observed with X-ray diffraction topography techniques. It was shown that the formation of void free grooved boundaries was feasible. In the cases when particulate contamination was prevented, the voids appeared in the grooved structures could be eliminated with annealing. Since it was found that the flattening was accompanied with plastic deformation, this deformation was suggested to be intensively involved in the process of void removal. A model was proposed explaining the interaction between the structural defects resulted in "a dissolution" of cavities. The described processes may occur in grooved as well as in smooth structures, but there are the former that allow to manage air traps and undesirable excess of dislocation density. Grooves can be paths for air leave. According to the established mechanisms, if not outdone, the dislocations form local defect arrangements at the grooves permitting the substantial reduction in defect density over the remainder of the interfacial area.

• Advances in nano research
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• v.2 no.1
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• pp.1-14
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• 2014

Dislocations are basic crystal defects and represent one-dimensional native nanostructures embedded in a perfect crystalline matrix. Their structure is predefined by crystal symmetry. Two-dimensional, self-organized arrays of such nanostructures are realized reproducibly using specific preparation conditions (semiconductor wafer direct bonding). This technique allows separating dislocations up to a few hundred nanometers which enables electrical measurements of only a few, or, in the ideal case, of an individual dislocation. Electrical properties of dislocations in silicon were measured using MOSFETs as test structures. It is shown that an increase of the drain current results for nMOSFETs which is caused by a high concentration of electrons on dislocations in p-type material. The number of electrons on a dislocation is estimated from device simulations. This leads to the conclusion that metallic-like conduction exists along dislocations in this material caused by a one-dimensional carrier confinement. On the other hand, measurements of pMOSFETs prepared in n-type silicon proved the dominant transport of holes along dislocations. The experimentally measured increase of the drain current, however, is here not only caused by an higher hole concentration on these defects but also by an increasing hole mobility along dislocations. All the data proved for the first time the ambipolar behavior of dislocations in silicon. Dislocations in p-type Si form efficient one-dimensional channels for electrons, while dislocations in n-type material cause one-dimensional channels for holes.