• Transactions of the Korean Society of Machine Tool Engineers
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• v.12 no.5
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• pp.59-66
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• 2003

This study suggests the new ultraprecision finishing techniques for micro die and mold parts using magnetic field-assisted polishing. Conventional magnetic abrasives have several disadvantages, which are missing of abrasive particle and inequal mixture between magnetic particle and abrasive particle. Therefore, bonded magnetic abrasive particles are fabricated by several method. For example, plasma melting and direct bonding. Carbonyl iron powder is used as magnetic particle there silicon carbide and alumina are abrasive particles. Developed magnetic abrasives are analyzed using SEM. Feasibility of magnetic abrasive and polishing performance of this magnetic abrasive particles also have been investigated. After polishing, surface roughness of workpiece is reduced from 85.4 ㎚ Ra to 9 ㎚ RA.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.102-102
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• 2018

Electronic industry had required the finer size and the higher performance of the device. Therefore, 3-D die stacking technology such as TSV (through silicon via) and micro-bump had been used. Moreover, by the development of the 3-D die stacking technology, 3-D structure such as chip to chip (c2c) and chip to wafer (c2w) had become practicable. These technologies led to the appearance of HBM (high bandwidth memory). HBM was type of the memory, which is composed of several stacked layers of the memory chips. Each memory chips were connected by TSV and micro-bump. Thus, HBM had lower RC delay and higher performance of data processing than the conventional memory. Moreover, due to the development of the IT industry such as, AI (artificial intelligence), IOT (internet of things), and VR (virtual reality), the lower pitch size and the higher density were required to micro-electronics. Particularly, to obtain the fine pitch, some of the method such as copper pillar, nickel diffusion barrier, and tin-silver or tin-silver-copper based bump had been utillized. TCB (thermal compression bonding) and reflow process (thermal aging) were conventional method to bond between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degrees. However, because of tin overflow which caused by higher operating temperature than melting point of Tin ($232^{\circ}C$), there would be the danger of bump bridge failure in fine-pitch bonding. Furthermore, regulating the phase of IMC (intermetallic compound) which was located between nickel diffusion barrier and bump, had a lot of problems. For example, an excess of kirkendall void which provides site of brittle fracture occurs at IMC layer after reflow process. The essential solution to reduce the difficulty of bump bonding process is copper to copper direct bonding below $300^{\circ}C$. In this study, in order to improve the problem of bump bonding process, copper to copper direct bonding was performed below $300^{\circ}C$. The driving force of bonding was the self-annealing properties of electrodeposited Cu with high defect density. The self-annealing property originated in high defect density and non-equilibrium grain boundaries at the triple junction. The electrodeposited Cu at high current density and low bath temperature was fabricated by electroplating on copper deposited silicon wafer. The copper-copper bonding experiments was conducted using thermal pressing machine. The condition of investigation such as thermal parameter and pressure parameter were varied to acquire proper bonded specimens. The bonded interface was characterized by SEM (scanning electron microscope) and OM (optical microscope). The density of grain boundary and defects were examined by TEM (transmission electron microscopy).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.65-72
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• 2005

We can integrate more IP blocks on a silicon die as the development of fabrication technologies and EDA tools. Consequently, we can design complicated SoC architecture including multi-processors. However, most of existing SoC buses have bottleneck in on-chip communication because of shared bus architectures, which result in the performance degradation of systems. In most cases, the performance of a multi-processor system is determined by efficient on-chip communication and the well-balanced distribution of computation rather than the performance of the processors. We propose an efficient SoC Network Architecture(SNA) using crossbar routers which provide a solution to ensure enough communication bandwidth. The SNA can significantly reduce the bottleneck of on-chip communication by providing multi-channels for multi-masters. According to the proposed architecture, we design a model system for the SNA. The proposed architecture has a better efficiency by $40\%$ than the AMBA AHB according to a simulation result.

• ETRI Journal
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• v.39 no.6
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• pp.866-873
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• 2017

We propose a multilayered-substrate-based power semiconductor discrete device package for a low switching loss and high heat dissipation. To verify the proposed package, cost-effective, low-temperature co-fired ceramic, multilayered substrates are used. A bare die is attached to an embedded cavity of the multilayered substrate. Because the height of the pad on the top plane of the die and the signal line on the substrate are the same, the length of the bond wires can be shortened. A large number of thermal vias with a high thermal conductivity are embedded in the multilayered substrate to increase the heat dissipation rate of the package. The packaged silicon carbide Schottky barrier diode satisfies the reliability testing of a high-temperature storage life and temperature humidity bias. At $175^{\circ}C$, the forward current is 7 A at a forward voltage of 1.13 V, and the reverse leakage current is below 100 lA up to a reverse voltage of 980 V. The measured maximum reverse current ($I_{RM}$), reverse recovery time ($T_{rr}$), and reverse recovery charge ($Q_{rr}$) are 2.4 A, 16.6 ns, and 19.92 nC, respectively, at a reverse voltage of 300 V and di/dt equal to $300A/{\mu}s$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.23-29
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• 2010

This paper presents a method for constructing a memory system using defective memory chips comprising faulty storage blocks. The three-dimensional memory system introduced here employs a die-stacked structure of faulty memory chips. Signals lines passing through the through-silicon-vias (TSVs) connect chips in the defect tolerant structure. Defective chips are classified into several groups each group comprising defective chips having faulty blocks at the same location. A defect tolerant memory system is constructed using chips from different groups. Defect-free storage blocks from spare chips replace faulty blocks using additional routing circuitry. The number of spare chips for defect tolerance is $s={\ulcorner}(k{\times}n)/(m-k){\urcorner}$ to make a system defect tolerant for (n+s) chips with k faulty blocks among m independently addressable blocks.

• Journal of Korea Foundry Society
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• v.36 no.6
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• pp.202-207
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• 2016

The effects of Fe and Si additions on the microstructures and mechanical properties of aluminum bronze have been investigated. In a bar-type specimen cast in a die mold, the addition of Fe promoted the dendritic solidification of the ${\alpha}$ phase. The hardness values increased slightly in the Fe-added specimen with heat treatment, while these values was increased significantly in the specimens with Si or with combined additions of Fe and Si. When a centrifugal casting bush with combined addition of Fe and Si was heat treated, the FeSi compound within the matrix was finely dispersed, and was observed to be the origin of cup-cone type conical dimple failure in the tensile fracture surface. The mechanical properties of the heat treated centrifugal casting bushes, whose nominal alloy compositions were (Cu-7.0Al-0.8Fe-3.0Si)wt%, exhibited tensile strength of $703-781N/mm^2$, elongation of 6.6-11.7% and hardness of Hv 222.6-249.2. These high values of strength and elongation were attributed to the strengthening of the matrix due to the combined addition of Fe and Si, and to precipitation of fine the FeSi compound.

• Tribology and Lubricants
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• v.31 no.4
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• pp.157-162
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• 2015

In this study, an ultrasonic nanocrystalline surface modification (UNSM) technique is applied to tungsten carbide-cobalt (WC-Co) to extend the service life of carbide parts used in press mold. The UNSM technique modifies the structure, reduces the surface roughness, increases the surface hardness, induces the compressive residual stress, and increases the wear resistance of materials by introducing severe plastic deformation. The surface roughness, hardness, and compressive residual stress of WC after UNSM treatment improve by about 42, 10, and 71%, respectively. A wear test under dry conditions is used to assess the effectiveness of the UNSM technique on the friction and wear behavior of WC. The UNSM technique is found to reduce the WC friction coefficient by approximately 21% and enhance the wear resistance by approximately 85%. The improved friction and wear behavior of WC may be mainly attributed to the increased hardness and compressive residual stress. Moreover, the WC specimen is treated by UNSM technique using three different WC, silicon nitride (Si₃N₄) and stainless steel (STS304) balls. The surface treated by WC balls shows the highest hardness when compared with treatment by stainless steel and silicon nitride balls. According to the obtained results, the UNSM technique is believed to increase the durability of the carbide component by improving the friction and wear behavior.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2007.05a
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• pp.417-420
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• 2007

Micro parts are usually used of producing by micro-electro-mechanical systems(MEMS). In this paper, we present some fundamental results concerning on the MEMS, extrusion condition on the micro forming characteristics and new micro forward extrusion machine has been developed. In the first step, we manufactured micro dies in two kinds of sections. One is a circle section, another is a cross section. The process for fabricating micro dies combines a deep UV-lithography, anisotropic etching techniques and metal electroplating with bulk silicon based on Ni with a thickness of $50{\mu}m$. The outer diameter of Ni-micro dies is 3mm and the diameter of extrusion section is $270{\mu}m$ for a cross section, $500{\mu}m$ for a circle section. The low linear density polyethylene(LLEPD) in the shape of a pellet has been used of micro extrusion. The billet was placed in a container manufactured by electric discharge machining and extruded through the micro die by a piezoelectric actuator. The micro extrusion has succeeded in a forming such micro parts as micro bars, micro cross shafts.