• Korean Journal of Metals and Materials
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• v.46 no.2
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• pp.69-79
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• 2008

A composition consisting of 10 nm-Ni/1 nm-Pd/(30 nm or 70 nm-poly)Si was thermally annealed using rapid thermal for 40 seconds at $300{\sim}1100^{\circ}C$ to improve the thermal stability of conventional nickel monosilicide. The annealed bilayer structure developed into $Ni(Pd)Si_x$, and the resulting changes in sheet resistance, microstructure, phase, chemical composition, and surface roughness were investigated. The silicide, which formed on single crystal silicon, could defer the transformation of $NiSi_2$, and was stable at temperatures up to $1100^{\circ}C$. It remained unchanged on polysilicon substrate compared with the sheet resistance of conventional nickel silicide. The silicides annealed at $700^{\circ}C$, formed on single crystal silicon and 30 nm polysilicon substrates exhibited 30 nm-thick uniform silicide layers. However, silicide annealed at $1,000^{\circ}C$ showed preferred and agglomerated phase. The high resistance was due to the agglomerated and mixed microstructures. Through X-ray diffraction analysis, the silicide formed on single crystal silicon and 30 nm polysilicon substrate, showed NiSi phase on the entire temperature range and mixed phases of NiSi and $NiSi_2$ on 70 nm polysilicon substrate. Through scanning probe microscope (SPM) analysis, we confirmed that the surface roughness increased abruptly until 36 nm on 30 nm polysilicon substrate while not changed on single crystal and 70 nm polysilicon substrates. The Pd-inserted nickel monosilicide could maintain low resistance in a wide temperature range and is considered suitable for nano-thick silicide processing.

• Korean Journal of Crystallography
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• v.12 no.2
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• pp.102-112
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• 2001

The mechanical properties of silicon crystals are important from the viewpoint of wafer and device fabrication processes. It is now widely recognized that silicon undergoes a series of phase transformations when subjected to high pressures, using conventional high pressure devices, such as diamond anvils or indenters. Diamond tip scratching on a silicon surface in the various conditions introduces various kinds of mechanical damage and stressed states. Micro Raman spectroscopy was used to observe the phase transition of single crystal silicon. As results, different morphologies were observed as functions of scratching speed and loading condition and various phases were observed as functions of scratching speed and loading condition.

• Korean Journal of Materials Research
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• v.16 no.9
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• pp.571-577
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• 2006

We fabricated thermal evaporated 10 nm-Ni/(poly)Si and 10 nm-Ni/1 nm-Ir/(poly)Si films to investigate the thermal stability of nickel monosilicide at the elevated temperatures by rapid annealing them at the temperatures of $300{\sim}1200^{\circ}C$ for 40 seconds. Silicides for salicide process was formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester is used for sheet resistance. Scanning electron microscope and field ion beam were employed for thickness and microstructure evolution characterization. An x-ray diffractometer and an auger depth profile scope were used for phase and composition analysis, respectively. Nickel silicides with iridium on single crystal silicon actives and polycrystalline silicon gates showed low resistance up to $1200^{\circ}C$ and $800^{\circ}C$, respectively, while the conventional nickel monosilicide showed low resistance below $700^{\circ}C$. The grain boundary diffusion and agglomeration of silicides led to lower the NiSi stable temperature with polycrystalline silicon substrates. Our result implies that our newly proposed Ir added NiSi process may widen the thermal process window for nano CMOS process.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.27 no.1
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• pp.57-63
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• 2017

High-purity ${\beta}-SiC$ powders for SiC single-crystal growth were synthesized by direct carbonization. The use of high-purity raw materials to improve the quality of a SiC single crystal is important. To grow SiC single crystals by the PVT method, both the particle size and the packing density of the SiC powder are crucial factors that determine the sublimation rate. In this study, we tried to produce high-purity ${\beta}-SiC$ powder with large particle sizes and containing low silicon by introducing a milling step during the direct carbonization process. Controlled heating improved the purity of the ${\beta}-SiC$ powders to more than 99 % and increased the particle size to as much as ${\sim}100{\mu}m$. The ${\beta}-SiC$ powders were characterized by SEM, XRD, PSA, and chemical analysis to assess their purity. Then, we conducted single-crystal growth experiments, and the grown 4H-SiC crystals showed high structural perfection with a FWHM of about 25-48 arcsec.

• Proceedings of the Korea Crystallographic Association Conference
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• 2001.05a
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• pp.21-21
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• 2001

• Proceedings of the Korea Crystallographic Association Conference
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• 2001.05a
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• pp.23-23
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• 2001

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.25 no.1
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• pp.13-19
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• 2015

Among the various possible factors affecting the Minority Carrier Life Time (MCLT) of the mc-Si crystal, dislocations formed during the cooling period after solidification were found to be a major element. It was confirmed that other defects such as grain boundary or twin boundary were not determinative defects affecting the MCLT because most of these defects seemed to be formed during the solidification period. With a measurement of total thickness variation (TTV) and bow of the silicon wafers, it was found that residual stress remaining in the mc-Si crystal might be another major factor affecting the MCLT. Thus, it is expected that better quality of mc-Si can be grown when the cooling process right after solidification is carried out as slow as possible.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.709-710
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• 2010

• Journal of the Korea Computer Industry Society
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• v.6 no.5
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• pp.757-766
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• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of the Semiconductor & Display Technology
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• v.2 no.4
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• pp.37-40
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• 2003

We have studied micro-machining technologies to fabricate parts and sensors used in the semiconductor equipment. The studies were based on the silicon integrated circuit processes, and composed of the anisotropic etching of single crystal silicon to fabricate a membrane structure for hot and cold junctions in the infrared absorber. KOH and TMAH were used as etching solutions for the anisotropic wet etching for membrane structure formation. The etching characteristic was observed for the each solution, and etching rate was measured depending upon the temperature and concentration of the etching solution. The different characteristics were observed according to pattern directions and etchant concentration. The pattern was made to incline $45^{\circ}$ on the primary flat, and optimum etching property was obtained in the case of 30 wt% and $90^{\circ}C$ of KOH etching solution for the formation of the membrane structure.