• Journal of Power System Engineering
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• v.5 no.4
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• pp.11-17
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• 2001

Micronization of sensor is a trend of the silicon sensor development with regard to a piezoresistive silicon pressure sensor, the size of the pressure sensor diaphragm have become smaller year by year, and a microaccelerometer with a size less than $200{\sim}300{\mu}m$ has been realized, In this paper, we study some of the bonding processes of SCS(single crystal silicon) insulator wafer for the microaccelerometer. and their subsequent processes which might affect thermal loads. The finite element method(FEM) has been a standard numerical modeling technique extensively utilized in micro structural engineering discipline for design of SCS insulator wafers. Successful temperature distribution analysis and design of the SCS insulator wafers based on the tunneling current concept using microaccelerometer depend on the knowledge about normal mechanical properties of the SCS and $SiO_2$ layer and their control through manufacturing processes.

• Korean Journal of Metals and Materials
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• v.47 no.11
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• pp.734-739
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• 2009

It is well known that the temperature and the flow pattern of the crystal-melt interface affect the qualities of the single crystal in the Czochralski process. Thus the temperature profile in the growth system is very important information. This work focuses on controlling the temperature of the silicon melt with a thermal gradient of the crucible. Therefore, the side heater is divided into three parts and an extra heater is added at the bottom for thermal gradient. The temperature of the silicon melt can be strongly influenced and controlled by the electric power of each heater.

• Korean Journal of Materials Research
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• v.17 no.4
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• pp.207-214
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• 2007

We fabricated thermally-evaporated 10 -Ni/(poly)Si and 10 -Ni/1 -Ir/(poly)Si structures to investigate the microstructure of nickel monosilicide at the elevated temperatures required for annealing. Silicides underwent rapid at the temperatures of 300-1200 for 40 seconds. Silicides suitable for the salicide process formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester was used to investigate the sheet resistances. A transmission electron microscope(TEM) and an Auger depth profile scope were employed for the determination of vertical section structure and thickness. Nickel silicides with iridium on single crystal silicon actives and polycrystalline silicon gates shoed low resistance up to 1000 and 800, respectively, while the conventional nickle monosilicide showed low resistance below 700. Through TEM analysis, we confirmed that a uniform, 20 -thick silicide layer formed on the single-crystal silicon substrate for the Ir-inserted case while a non-uniform, agglomerated layer was observed for the conventional nickel silicide. On the polycrystalline silicon substrate, we confirmed that the conventional nickel silicide showed a unique silicon-silicide mixing at the high silicidation temperature of 1000. Auger depth profile analysis also supports the presence of thismixed microstructure. Our result implies that our newly proposed iridium-added NiSi process may widen the thermal process window for the salicide process and be suitable for nano-thick silicides.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.4
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• pp.308-317
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• 2007

We fabricated thermally-evaporated 10 nm-Ni/(poly)Si and 10 nm-$Ni_{0.5}Co_{0.5}$/(Poly)Si structures to investigate the microstructure of nickel silicides at the elevated temperatures required lot annealing. Silicides underwent rapid annealing at the temperatures of $600{\sim}1100^{\circ}C$ for 40 seconds. Silicides suitable for the salicide process formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester was used to investigate the sheet resistances. A transmission electron microscope and an Auger depth profilescope were employed for the determination of vortical microstructure and thickness. Nickel silicides with cobalt on single crystal silicon actives and polycrystalline silicon gates showed low resistance up to $1100^{\circ}C$ and $900^{\circ}C$, respectively, while the conventional nickle monosilicide showed low resistance below $700^{\circ}C$. Through TEM analysis, we confirmed that a uniform, $10{\sim}15 nm$-thick silicide layer formed on the single-crystal silicon substrate for the Co-alloyed case while a non-uniform, agglomerated layer was observed for the conventional nickel silicide. On the polycrystalline silicon substrate, we confirmed that the conventional nickel silicide showed a unique silicon-silicide mixing at the high silicidation temperature of $1000^{\circ}C$. Auger depth profile analysis also supports the presence of this mixed microstructure. Our result implies that our newly proposed NiCo-alloy composite silicide process may widen the thermal process window for the salicide process and be suitable for nano-thick silicides.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.15 no.2
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• pp.45-50
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• 2005

During oxidation process, several type of defects are formed on the surface of the silicon crystal which was damaged mechanically before oxidation. As the size of abrasive particle increases multiple dislocation loops are produced favorably over oxidation-induced stacking faults, which are dominantly produced when ground with finer abrasive particle. These defects are not related with the crystal growth process like Czochralski or directional solidification. During directional solidification process, twins and stacking faults are the two major defects observed in the bulk of the silicon crystal. On the other hand, slip dislocations produced by the thermal stress are not observed. Thus, not only in single crystalline silicon crystal but also in multi-crystalline silicon, extrinsic gettering process with programmed production of surface defects might be highly applicable to silicon wafers for purification.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.20 no.10
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• pp.3113-3125
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• 1996

The objective of this study is to develop novel method named mechanical and chemical machining technique, which is capable of producing three dimensional patterns of few micrometers in dimension on a silicon wafer without the use of a mask. The strategy is to impart mechanical energy along the path of the pattern to be fabricated on a single crystal silicon by way on introdusing frictional interaction under controlled conditions. Then, the surface is preferentially etched to reveal the areas that have been mechanically energized. Upon completion of the etching process, the three dimensional pattern is produced on the silicon surface. Experiments have been conducted to identify the optimal tool material, geometery, as well as fabrication condition. The new technique introduced in this paper is significantly simpler than the conventional method which require sophisticated equipment and much time.

• Journal of Korean Vacuum Science & Technology
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• v.1 no.1
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• pp.1-12
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• 1997

A new three-dimensional (3D) Monte Carlo ion implantation simulator, TRICSI, has been developed to investigate 3D mask effects in the typical mask structure for ion implantation into crystalline silicon. We present the mask corner and mask size effects of implanted boron range profiles, and also show the calculated damage distributions by applying the modified Kinchin-Pease equation in the single-crystal silicon target. The simulator calculates accurately and efficiently the implanted-boron range profiles under the relatively large implanted area, using a newly developed search algorithm for the collision partner in the single-crystal silicon. All of the typical implant parameters such as dose, tilt and rotation angles, in addition to energy can be used for the 3D simulation of ion implantation.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.32 no.1
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• pp.1-6
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• 2022

In this research, a ring-shaped silicon carbide (SiC) single crystal manufactured using the PVT (Physical Vapor Transport) method was proposed to be applied to a SiC focus ring in semiconductor etching equipment. A cylindrical graphite structure was placed inside the graphite crucible to grow a ring-shaped SiC single crystal by the PVT method. SiC single crystal ring without crack was successfully obtained in case of using SiC single crystal wafer as a seed. A plasma etching process was performed to compare plasma resistance between the CVD-SiC focus ring and the PVT-SiC focus ring. The etch rate of ring materials in PVT-single crystal SiC focus ring was definitely lower than that of CVD-SiC focus ring, indicating better plasma resistance of PVT-SiC focus ring.

• Journal of Mechanical Science and Technology
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• v.15 no.12
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• pp.1876-1881
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• 2001

We present the numerical analysis of the growth of a silicon (Si) single crystal. In the MCZ (Magnetic-field-applied Czochralski) method, two magnetic fields that stand opposite to each other generate a cusp magnetic field. In this work, the three cusp magnetic fields used for the analysis are an extern magnetic field, a surface magnetic field and an internal magnetic field. Each case was evaluated mainly as to the degree of stirring, shaft symmetry and the stability of the flow. As a result, the cusp magnetic field that yielded to best conditions was the internal magneic field.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.18 no.5
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• pp.191-194
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• 2008

We will focus on the horizontal Bridgman growth system to analyze the transport phenomena numerically, because the simple furnace system and the confined growth environment allow for the precise understanding of the transport phenomena in solidification process. In conventional melt growth process, the dopant concentration tends to vary significantly along the crystal. In this work, we propose the modification of crucible geometry for improving the productivity of silicon single-crystal growth by controlling axial specific resistivity distribution. Numerical analysis has been performed to study the transport phenomena of dopant impurities in conventional and proposed Bridgman silicon growth using the finite element method and implicit Euler time integration. It has been demonstrated using mathematical models and by numerical analysis that proposed method is useful for obtaining crystals with superior uniformity along the growth direction at a lower cost than can be obtained by the conventional melt growth process.