• Journal of the Microelectronics and Packaging Society
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• v.7 no.1
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• pp.7-12
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• 2000

As an essential technology for the FED, VFD and PDP packaging having merits of no glass frit and no glass tube usage, two sodalime glass substrates were electrostatically-bonded in a vacuum environment, and the bond properties were compared with the case of bonding in atmosphere. The glass wafer pairs bonded in vacuum using a-Si interlayer had a relatively lower bond strength than the ones bonded in atmosphere under same bonding conditions (temperature and voltage). And the bond strength was increased in the case of oxygen ambient. Through the XPS and SIMS analyses fur the surface region of a-silicon and bulk glass, it might be concluded that the lower bonding strength was originated from the inactive silicon oxide growth occurred during the electrostatic bonding process due to oxygen deficiency in vacuum.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.3
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• pp.134-142
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• 1995

We discovered that each distinct shape of the roof-shaped peaks of (111) facets, which are generated on (110) cross-section of the directly bonded (100) silicon wafer pairs after KOH etching, can be mapped to one of three conditions of the interfacial oxide existing at the bonding interface as follows. That is, thick solid line can be mapped to stabilization, thin solid line to disintegration, and thin broken line to spheroidization. also we confirmed that most of the interfacial oxides of a well-aligned wafer pairs were disintegrated and spheroidized through high-temperature annealing process above 900$^{\circ}$C while the oxide was stabilized persistently when two wafers are bonded rotationally around their common axis perpendicular to the wafer planes.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1440-1441
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• 1995

We fabricated diode-type silicon field emitter array device and tested the current-voltage characteristics. Silicon oxide layer having the thickness of $1{\mu}m$ is grown in the (100) oriented n-type silicon substrates. Oxide layer is patterned by the mask with $10{\mu}m$ diameter circles. Silicon substrate is then etched using NAF 1 solution to form the sharp tip arrays as an electron source. In the UHV test station, we tested the current-voltage characteristics for the samples. Turn-on voltage was about 140V and maximum emission current was $310{\mu}A$ at 164V. We studied about silicon bonding process for future work, too.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.10
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• pp.857-863
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• 2014

In this work, we introduce various bonding technologies for 3D package and suggest Insert-Bump bonding (ISB) process newly to stack multi-layer chips successively. Microstructure of Insert-Bump bonding (ISB) specimens is investigated with respect to bonding parameters. Through experiments, we study on find optimal bonding conditions such as bonding temperature and bonding pressure and also evaluate in the case of fluxing and no-fluxing condition. Although no-fluxing bonding process is applied to ISB bonding process, good bonding interface at $270^{\circ}C$ is formed due to the effect of oxide layer breakage.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.921-926
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• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

• ETRI Journal
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• v.17 no.4
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• pp.1-12
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• 1996

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current ($I_{DS}-V_{DS}$) curves, substrate resistance effect on the $I_{DS}-V_{DS}$ curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.

• Korean Journal of Materials Research
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• v.16 no.10
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• pp.652-655
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• 2006

A direct wafer bonding process necessary for GaAs-on-insulator (GOI) fabrication with high thermal annealing temperatures was studied by using PECVD oxides between gallium arsenide and silicon wafers. In order to apply some uniform pressure on initially-bonded wafer pairs, a graphite sample holder was used for wafer bonding. Also, a tool for measuring the tensile forces was fabricated to measure the wafer bonding strengths of both initially-bonded and thermally-annealed samples. GaAs/$SiO_2$/Si wafers with 0.5-$\mu$m-thick PECVD oxides were annealed from $100^{\circ}C\;to\;600^{\circ}C$. Maximum bonding strengths of about 84 N were obtained in the annealing temperature range of $400{\sim}500^{\circ}C$. The bonded wafers were not separated up to $600^{\circ}C$. As a result, the GOI wafers with high annealing temperatures were demonstrated for the first time.

• Journal of the Korean institute of surface engineering
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• v.29 no.5
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• pp.482-486
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• 1996

The progress of microelectronics technology has been requiring agressive developments of device technologies. Also the requirements of the next generation devices is heading to the limits of their functions and materials, and hence asking the very specific silicon wafer such as SOI(Silicon On Insulator) wafer. The talk covers the dome stic and world-wide status of SOI device developments and applications. The presentation will also touch some predictions such as SOI device prgress schedules, impacts on the normal wafer developments, market sizes, SOI wafer prices, and so on. Finally it will cover technical aspects which are silicon oxide conditions for bonding, point defects and, surface contaminations. These points will be hopefully overcome by involved people in microelectronics industry.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.2
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• pp.114-119
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• 2000

Etch characteristics of SF6/CI2 electron cyclotron resonance (ECR) plasmas have been investigated. Surface reaction of gas plasma with polysilicon was also analysed using X-ray photoelectron spectroscopy (XPS). At the same time, the relationship between surface reaction and the etched profile of polysilicon was examined using XPS. The etch rate of polysilicon and oxide increases with increasing flow rate of SF6 in the SF6/CI2 gas mixture, and tis selectivity also increase also increase. It was also found that as increasing flow rate of SF6 in the SF6/CI2 gas mixture, the atomic% of chlorine detected at surface region decrease, but F and S contents increase. At the same time, when the mixing ratio of SF6 gas increases, the anisotropy of etched polysilicon is sharply decreased in the 0%~10% range of the SF6 mixing ratio, but is rarely varied in the range over 10%, in spite of the large variations in flow rates. It can be explained that the bonding of S-Si due to SiSx(x$\leq$2) compound formed on the etched surface suppress the formation of Si-Cl and 'or Si-F bonding in the silicon etching.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1057-1059
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• 1993

Some interested phenomena, which were appeared near the bonding interface, were investigated by angle lapping and delineation method, SEM, and TEM observations. Voids, defects, material continuity, and interfacial oxide stability were observed and discussed in the fusion-bonded Bi-Si or Si-$SiO_2$/Si wafer pairs.