• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.44.2-44.2
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• 2009

Polycrystalline materials suchas yttria and alumina have been applied as a plasma resisting material for the plasma processing chamber. However, polycrystal line material may easily generate particles and the particles are sources of contamination during the plasma enhanced process. Amorphous material can be suitable to prevent particle generation due to absence of grain-boundaries. We manufactured nitrogen-containing $SiO_2-Al_2O_3-Y_2O_3$ based glasses with various contents of silicon and fixed nitrogen content. The thermal properties, mechanical properties and plasma etching rate were evaluated and compared for the different composition samples. The plasma etching behavior was estimated using XPS with depth profiling. From the result, the plasma etching rate highly depends on the silicon content and it may results from very low volatile temperature of SiF4 generated during plasma etching. The silicon concentration at the plasma etched surface was very low besides the concentration of yttrium and aluminum was relatively high than that of silicon due to high volatile temperature of fluorine compounds which consisted with aluminum and yttrium. Therefore, we conclude that the samples having low silicon content should be considered to obtain low plasma etching rate for the plasma resisting material.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.112-116
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• 2000

This paper presents anisotropic ethcing characteristics of single-crystal silicon in tetramethylammonium hydroxide(TMAH):isopropyl alcohol(IPA) solutions containing pyrazine. With the addition of IPA to TMAH solutions, etching characteristics are exhibited that indicate an improvement in flatness on the etching front and a reduction in undercutting, but the etch rate on (100) silicon is decreased. The (100) silicon etch rate is improved by the addition of pyrazine. An etch rate on (100) silicon of $0.8\;{\mu}m/min$, which is faster by 13 % than a 20 wt.% solution of pure TMAH, is obtained using 20 wt.% TMAH:0.5 g/100 ml pyrazine solutions, but the etch rate on (100) silicon is decreased if more pyrazine is added. With the addition of pyrazine to a 25 wt.% TMAH solution, variations in flatness on the etching front were not observed and the undercutting ratio was reduced by 30 ~ 50 %.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.5
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• pp.364-369
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• 2011

Analyzing electrical degradation of polycrystalline silicon transistor to applicable at several environment is very important issue. In this research, after fabricating p channel poly crystalline silicon TFT (thin film transistor) electrical characteristics were compare and analized that changed by gate bias with first measurement. As a result on and off current was reduced by variation of gate bias and especially re duce ratio of off current was reduced by $7.1{\times}10^1$. On/off current ratio, threshold voltage and electron mobility increased. Also, when channel length gets shorter on/off current ratio was increased more and thresh old voltage increased less. It was cause due to electron trap and de-trap to gate silicon oxide by variation of gate bias.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.235-235
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• 2010

The Anti-reflection coating(ARC) properties can be formed on silicon substrate using a simple electrochemical etching technique. This etching step can be improve solar cell efficiency for a solar cell manufacturing process. This paper is based on the removal of silicon atoms from the surface a layer of porous silicon(PSi). Porous silicon is form by anodization and can be obtained in an electrolyte with hydrofluoric. It have demonstrated the feasibility of a very efficient porous Si layer, prepared by a simple, cost effective, electrochemical etching method. We expect our research can results approaching to lower than 10% of reflectance by optimization of process parametaer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.04b
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• pp.121-124
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• 2004

The research on the porous silicon having low wafer stress during the oxidation process in IPOS(Isolation by Porous Oxidized Silicon) were carried out. Fine pores with less than 100A of diameter were found in the porous silicon which from p-type Si by electrochemical etching. In this study, it is possible to make the porous silicon with 59% of porosity.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.255-257
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• 2001

In this paper, the silicon rubber insulator for transmission line was experimented for 1,000 hours aging test in salt-fog condition. To evaluate and examine the aging properties of silicon rubber insulator for test, the leakage current of surface was measured. Also hydrophobicity and scanning electron microscopy were compared with initial and aged sample respectively. Above results, we can confirm that the surface properties of silicon rubber insulator easily aged by salt-fog condition.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1165-1174
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• 2003

The responses of hypothetical silicon nanotubes under torsion have been investigated using an atomistic simulation based on the Tersoff potential. A torque, proportional to the deformation within Hooke's law, resulted in the ribbon-like flattened shapes and eventually led to a breaking of hypothetical silicon nanotubes. Each shape change of hypothetical silicon nanotubcs corresponded to an abrupt energy change and a singularity in the strain energy curve as a function of the external tangential force, torque, or twisted angle. The dynamics o silicon nanotubes under torsion can be modelled in the continuum elasticity theory.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.2
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• pp.125-130
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• 2000

Two step growth of reduced pressure chemical vapor eposition has been successfully developed to achieve in-situ phosphorus-doped silicon epilayers, and the characteristic evolution on their microstructures has been investigated using scanning electron microscopy, transmission electron microscopy, and secondary ion mass spectroscopy. The two step growth, which employs heavily in-situ P doped silicon buffer layer grown at low temperature, proposes crucial advantages in manipulating crystal structures of in-situ phosphorus doped silicon. In particular, our experimental results showed that with annealing of the heavily P doped silicon buffer layers, high-quality epitaxial silicon layers grew on it. the heavily doped phosphorus in buffer layers introduces into native oxide and plays an important role in promoting the dispersion of native oxides. Furthermore, the phosphorus doping concentration remains uniform depth distribution in high quality single crystalline Si films obtained by the two step growth.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.21-21
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• 2007

Strained silicon 기술은 MOSFET 채널 내 캐리어 이동도를 향상시켜 집적회로의 성능을 향상시키는 기술이다. 최근에는 strained 실리콘 기술과 SOI(silicon On Insulator) 기술을 접목시켜 집적회로 소자의 특성을 더욱 향상시킨 SSOI(Strained Silicon On Insulator) 기술이 연구되고 있다. 본 연구에서는 pseudo MOSFET 측정법을 이용하여 strained SOI 웨이퍼의 전기적 특성 분석을 행하였다. pseudo MOSFET 측정법은 SOI 웨이퍼의 전기적 특성분석을 위해 고안된 방법으로써 산화, 도핑 등의 소자 제조 공정 없이도 SOI 표면 실리콘층의 이동도와 매몰산화막과의 계면 특성 등을 분석해 낼 수 있는 기술이다. 표면 실리콘층의 두께와 매몰산화막의 두께가 각각 60nm, 150nm인 SOI 웨이퍼와 동일한 막 두께를 가지며 표면 실리콘층이 strained silicon인 SSOI 웨이퍼를 제작하여 그 특성을 비교 분석하였다. Pseudo MOSFET 측정 결과 Strained SOI 웨이퍼에서 표면 실리콘총 내의 전자 이동도가 일반적인 SOI 웨이퍼보다 약 25% 향상되었으며 정공 이동도나 매몰산화막의 계면 트랩밀도는 큰 차이를 보이지 않았다.

• Journal of Electrochemical Science and Technology
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• v.2 no.3
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• pp.168-173
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• 2011

The availability, low toxicity, and high degree of technological development make silicon the most likely material to be used in solar cells, the cost of solar cells depends entirely on cost of high purity silicon production. The present work was conducted to electrodeposite of silicon from $K_2SiF_6$, an inexpensive raw material prepared from fluorosilicic acid ($H_2SiF_6$) produced in Iraqi Fertilizer plants, and using inexpensive graphite material as cathode electrode. The preparation of potassium fluorosilicate was performed at ($60^{\circ}C$) in a three necks flask provided with a stirrer, while the electro deposition was performed at $750^{\circ}C$ in a three-electrodes configuration with melt containing in graphite pot. High purity potassium fluorosilicate (99.25%) was obtained at temperature ($60^{\circ}C$), molar ratio-KCl/$H_2SiF_6$(1.4) and agitation (600 rpm). Spongy compact deposits were obtained for silicon with purity not less than (99.97%) at cathode potential (-0.8 V vs. Pt), $K_2SiF_6$ concentration (14% mole percent) with grain size (130 ${\mu}m$) and level of impurities (Cu, Fe and Ni) less than (0.02%).