• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.864-867
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• 2003

Since the development of semiconductors, various related research has been conducted. During research, silicon diodes have been commonly used because of their simplicity and low cost in the manufacturing process. This research deals with p-n junction threshold voltages from silicon diodes due to transport current at a cryogenic temperature. At a cryogenic temperature(77K) we could get minimum current which junction threshold voltage becomes constant. This is experimented on GPIB communication and it consist of programmable current source, multimeter which gauge the threshold voltage in a very low temperature caused by transport current from 5nA to 1mA and $LN_2$(77K) for coolant. This experiment is programmed all process using Measurement studio(Lab window) tool.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.5
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• pp.353-357
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• 2010

Recently, silicon etching have received much attention for display industry, nano imprint technology, silicon photonics, and MEMS application. After the etching process, removing of etch mask and residue of sidewall is very important. The investigation of the etched mask removing was carried out by using the ashing, HF dipping and acid cleaning process. Experiment shows that oxygen component of reactive gas and photoresist react with silicon and converting them into the mask fence. It is very difficult to remove by using ashing or acid cleaning process because mask fence consisted of Si and O compounds. However, dilute HF dipping is very effective process for SiOx layer removing. Finally, we found optimized condition for etched mask removing.

• Journal of the Korean Ceramic Society
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• v.46 no.6
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• pp.685-688
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• 2009

Surface Texturing is very important process for high cell efficiency in crystalline silicon solar cell. Anisotropic texturing with an alkali etchant was known not to be able to produce uniform surface morphology in multi-crystalline silicon (mc-Si), because of its different etching rate with random crystal orientation. In order to reduce surface reflectance of mc-Si wafer, the general etching tendency was studied with HF/HN$O_3$/De-ionized Water acidic solution. And the surface structures of textured mc-Si in various HF/HN$O_3$ ratios were compared. The surface morphology and reflectance of textured silicon wafers were measured by FE-SEM and UVvisible spectrophotometer, respectively. We obtained average reflectance of $16{\sim}19$% for wavelength between 400 nm and 900 nm depending on different etching conditions.

• Proceedings of the KSME Conference
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• 2001.06a
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• pp.151-156
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• 2001

Experimental frictional and wear characteristics of silicon graphite materials is studied in this paper. Those specimens are lubricated with high temperature and highly pressurized water to simulate the same operating condition for the journal bearing and the thrust bearing on the main coolant pump bearing in the newly developing nuclear reactor named SMART(System-integrated Modular Advanced ReacTor). Operating condition of the bearings is realized by the tribometer and the autoclave. Friction coefficient and wear loss are analyzed to choose the best silicon graphite material. Pin on plate test specimens are used and coned disk springs are used to control the applied force on the specimens. Wear loss ana wear width are measured by a precision balance and a micrometer. The friction force is measured by the strain gauge which can be used under high temperature and high pressure. Three kinds of silicon graphite materials are examined and compared with each other, and each material shows similar but different results on frictional and wear characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.175-177
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• 2002

Electrical characteristics of the Si-O superlattice diode as a function of annealing conditions have been studied. The nanocrystalline silicon/adsorbed oxygen superlattice formed by molecular beam epitaxy (MBE) system. Consequently, the experimental results of superlattice diode with multilayer Si-O structure showed the stable and good insulating behavior with high breakdown voltage. This is very useful promise for Si-based optoelectronic and quantum device as well as for the replacement of silicon-on-insulator (SOI) in ultra high speed and lower power CMOS devices in the future, and it can be readily integrated with silicon ULSI processing.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.202-205
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• 2002

The photoluminescence (PL) characteristics of the silicon-oxygen(Si-O) superlattice formed by molecular beam epitaxy (MBE) were studied. To confirm the presence of the nanocrystalline Si structure, Raman scattering measurement was performed. The blue shift was observed in the PL peak of the oxygen-annealed sample, compared to the hydrogen-annealed sample, which is due to a contribution of smaller crystallites. Our results determine the right direction for the fabrication of silicon-based optoelectronic and quantum devices as well as for the replacement of silicon-on-insulator (SOI) in high-speed and low-power silicon MOSFET devices in the future.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.8
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• pp.455-460
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• 2016

A textured front surface is required in high efficiency silicon solar cells to reduce reflectance and to improve light trapping. Wet etching with alkaline solution is usually applied for mono crystalline silicon solar cells. However, alkali texturing method is not appropriate for multi-crystalline silicon wafers due to grain boundary of random crystallographic orientation. Accordingly, acid texturing method is generally used for multi-crystalline silicon wafers to reduce the surface reflectance. To reduce reflectivity of multi-crystalline silicon wafers, double texturing method with combination of acid and reactive ion etching is an attractive technical solution. In this paper, we have studied to optimize RIE condition by different RF power condition (100, 150, 200, 250, 300 W).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.12
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• pp.750-758
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• 2016

For the channel doping of shallow junction and retrograde well formation in CMOS, indium can be implanted in silicon. The retrograde doping profiles can serve the needs of channel engineering in deep MOS devices for punch-through suppression and threshold voltage control. Indium is heavier element than B, $BF_2$ and Ga ions. It also has low coefficient of diffusion at high temperatures. Indium ions can be cause the erode of wafer surface during the implantation process due to sputtering. For the ultra shallow junction, indium ions can be implanted for p-doping in silicon. UT-MARLOWE and SRIM as Monte carlo ion-implant models have been developed for indium implantation into single crystal and amorphous silicon, respectively. An analytical tool was used to carry out for the annealing process from the extracted simulation data. For the 1D (one-dimensional) and 2D (two-dimensional) diffused profiles, the analytical model is also developed a simulation program with $C^{{+}{+}}$ code. It is very useful to simulate the indium profiles in implanted and annealed silicon autonomously. The fundamental ion-solid interactions and sputtering effects of ion implantation are discussed and explained using SRIM and T-dyn programs. The exact control of indium doping profiles can be suggested as a future technology for the extreme shallow junction in the fabrication process of integrated circuits.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.4
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• pp.328-332
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• 2011

The formation of front metal contact silicon solar cells is required for low cost, low contact resistance to silicon surface. One of the front metal contacts is Ni/Cu plating that it is available to simply and inexpensive production to apply mass production. Ni is shown to be a suitable barrier to Cu diffusion into the silicon. The process of Ni electroless plating on front silicon surface is performed using a chemical bath. Additives and buffer agents such as ammonium chloride is added to maintain the stability and pH control of the bath. Ni deposition rate is found to vary with temperature, time, utilization of bath. The experimental result shown that Ni layer by SEM (scanning electron microscopy) and EDX analysis. Finally, plated Ni/Cu contact solar cell result in an efficiency of 17.69% on $2{\times}2\;cm^2$, Cz wafer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.6
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• pp.321-326
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• 2016

Minimizing the carrier recombination and electrical loss through surface passivation is required for high efficiency c-Si solar cell. Usually, $SiN_X$, $SiO_X$, $SiON_X$ and $AlO_X$ layers are used as passivation layer in solar cell application. Silicon oxide layer is one of the good passivation layer in Si based solar cell application. It has good selective carrier, low interface state density, good thermal stability and tunneling effect. Recently tunneling based passivation layer is used for high efficiency Si solar cell such as HIT, TOPCon and TRIEX structure. In this paper, we focused on silicon oxide grown by various the method (thermal, wet-chemical, plasma) and passivation effect in c-Si solar cell.