• Restorative Dentistry and Endodontics
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• v.32 no.4
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• pp.343-355
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• 2007

The objectives of this study was to evaluate the durability of 4 resin cements by means of microtensile bond strength test combined with thermocycling method and fractographic FE-SEM analysis. Experimental groups were prepared according to thermocycling (0, 1,000, 5,000) and the kind of resin cements, those were Variolink II, Multilink, Panavia F 2.0, Rely X Unicem. Flat dentin surfaces were created on mid-coronal dentin of extracted third molars. Then fresh dentin surface was grounded with 320-grit silicon carbide abrasive papers to create uniform smear layers. Indirect composite block (Tescera, Bisco Inc., Schaumburg, IL, USA) was fabricated ($12\;{\times}\;12\;{\times}\;6\;mm^3$). It's surface for bonding to tooth was grounded with silicon carbide abrasive papers from 180- to 600-grit serially, then sandblasted witk $20\;-\;50\;{\mu}m$ alumina oxide. According to each manufacturer's instruction, dentin surface was treated and indirect composite block was luted on it using each resin cement. For Rely X Unicem, dentin surface was not treated. The bonded tooth-resin block were stored in distilled water at $37^{\circ}C$ for 24 hours. After thermocycling, the bonded tooth-resin block was sectioned occluso-gingivally to 1.0 mm thick serial slabs using all Isomet slow-speed saw (Isomet, Buehler Ltd, Lake Bluff, IL, USA). These sectioned slabs were further sectioned to $1.0\;{\times}\;1.0\;mm^2$ composite-dentin beams. The specimens were tested with universal testing machine (EZ-Test, Shimadzu, Japan) at a crosshead speed of 1.0 mm/min with maximum load of 500 N. The data was analyzed using one-way ANOVA and Duncan's multiple comparison test at $p\;{\leq}\;0.05$ level. Within the limited results, we conclude as follows; 1. The bond strength of Variolink II was evaluated the highest among experimental groups and was significantly decreased after 1,000 thermocycling (p < 0.05). 2. The bond strength of Multilink was more affected by thermocycling than the other experimental groups and significantly decreased after 1,000 thermocycling (p < 0.05). 3. Panavia F 2.0 and Rely X Unicem showed the gradually decreased tendency of microtensile bond strength according to thermocycling but there was no significant difference (p > 0.05). 4. Adhesive based-resin cements showed lower bond strength with or without thermocycling than composite based-resin cements. 5. Variolink II & Multilink showed high bond strength and mixed failure, which was occurred with a thin layer of luting resin cement before thermocycling and gradually increased adhesive failure along the dentin surface after thermocycling. The bonding performance of resin cement can be affected by application procedure and chemical composition. Composite based-resin cement showed higher bond strength and durability than adhesive based-resin cement.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.270-275
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• 2012

This paper describes design of a variable-N frequency synthesizer for RF PLL with $0.13{\mu}m$ silicon CMOS technology being used as an application of the UWB system like MBOA. To get good performance of speed and noise super dynamic circuits was used, and to get variable-N division ratio MOSFET switching circuits was used. Especially to solve narrow bandwidth problem of the dynamic circuits load resistance value of unit divider block was varied. Simulation results of the designed circuit shows very fast and wide operation characteristics as 5~26GHz frequency range.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.56-61
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• 2011

This paper describes design of a programmable frequency synthesizer for RF PLL with $0.18{\mu}m$ silicon CMOS technology being used as an application of the UWB system like MBOA. To get good performance of speed and noise super dynamic circuits was used, and to get programmable division ratio switching circuits was used. Especially to solve narrow bandwidth problem of the dynamic circuits load resistance value of unit divider block was varied. Simulation results of the designed circuit shows very fast and wide operation characteristics as 1~14GHz frequency range.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.11
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• pp.1962-1969
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• 2008

According to the increase of power demand and expansion of downtown, it is necessary to install transformers additionally in operating substations and construct substations in residential area. But the public complaint is increased due to the transformer noise of the substation. KEPCO has used a vibration preventing pad, various soundproof walls and an encloser to transformers in outdoor substations, and a soundproof door, shutter and wind-path soundproof equipment in indoor substations to block the sound propagation of the transformers. But these noise reduction methods are not satisfied. It should be considered to reduce transformer noise itself. In this paper, we investigated core noise reduction techniques to develope a low noise transformer. The techniques to reduce core noise of the transformer are application of high permeability grain oriented silicon sheets, decrease of magnetic flux density of core, application of 6step-lap core stacking method, improvement of core binding method(binding addition, band fixing) and application of rubber damper in oder to reduce transmission of core vibration, etc.

• Journal of information and communication convergence engineering
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• v.12 no.3
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• pp.186-192
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• 2014

Monolithic three-dimensional integrated chips (3D ICs) are an emerging technology that offers an integration density that is some orders of magnitude higher than the conventional through-silicon-via (TSV)-based 3D ICs. This is due to a sequential integration process that enables extremely small monolithic inter-tier vias (MIVs). For a monolithic 3D memory, we first explore the static random-access memory (SRAM) design. Next, for digital logic, we explore several design styles. The first is transistor-level, which is a design style unique to monolithic 3D ICs that are enabled by the ultra-high-density of MIVs. We also explore gate-level and block-level design styles, which are available for TSV-based 3D ICs. For each of these design styles, we present techniques to obtain the graphic database system (GDS) layouts, and perform a signoff-quality performance and power analysis. We also discuss various challenges facing monolithic 3D ICs, such as achieving 50% footprint reduction over two-dimensional (2D) ICs, routing congestion, power delivery network design, and thermal issues. Finally, we present design techniques to overcome these challenges.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04b
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• pp.37-38
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• 2009

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics. It is known that in SiC power MOSFET, the JFET region width is one of the most important parameters. In this paper, we demonstrated that the switching performance of DMOSFET is dependent on the with width of the JFET region by using 2-D Mixed-mode simulations. The 4H-SiC DMOSFETs with a JFET region designed to block 800 V were optimized for minimum loss by adjusting the parameters of the n JFET region, CSL, and n-drift layer. It has been found that the JFET region reduces specific on-resistance and therefore the switching characteristics depend on the JFET region.

• Bulletin of the Korean Chemical Society
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• v.24 no.3
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• pp.325-333
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• 2003

An analysis of the electronic structure and bonding in the ternary silicide YNiSi₃is made, using extended Huckel tight-binding calculations. The YNiSi₃structure consists of Ni-capped Si₂dimer layers and Si zigzag chains. Significant bonding interactions are present between the silicon atoms in the structure. The oxidation state formalism of $(Y^{3+})(Ni^0)(Si^3)^{3-}$ for YNiSi₃constitutes a good starting point to describe its electronic structure. Si atoms receive electrons from the most electropositive Y in YNiSi₃, and Ni 3d and Si 3p states dominate below the Fermi level. There is an interesting electron balance between the two Si and Ni sublattices. Since the ${\pi}^*$ orbitals in the Si chain and the Ni d and s block levels are almost completely occupied, the charge balance for YNiSi₃can be rewritten as $(Y^{3+})(Ni^{2-})(Si^{2-})(Si-Si)^+$, making the Si₂layers oxidized. These results suggest that the Si zigzag chain contains single bonds and the Si₂double layer possesses single bonds within a dimer with a partial double bond character. Strong Si-Si and Ni-Si bonding interactions are important for giving stability to the structure, while essentially no metal-metal bonding exists at all. The 2D metallic behavior of this compound is due to the Si-Si interaction leading to dispersion of the several Si₂π bands crossing the Fermi level in the plane perpendicular to the crystallographic b axis.

• Restorative Dentistry and Endodontics
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• v.15 no.1
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• pp.67-80
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• 1990

This study was performed for elucidating the effects on surface polishing of composite resins. In this study, Silux(microfilled), Graft(hybrid), Bisfil- I (hybrid posterior) and Hi-pol(conventional) were used. Sixty specimens were made with 4 brands of composite resins and Optilux system in $2.0{\times}1.3{\times}1.0cm$ resin block which has a cavity with 0.5cm diameter and 0.5cm depth. Polishing was done with #600 sand paper and Soflex, Super-snap, Micron finishing system, or Composite polishing kit. Final polished surfaces were measured by roughness tester(Kasaka Lab. Ltd., Japan) and image analyser(Omnimet Image Analyser, Buehler, USA). The results were as follows, 1. The celluloid strip produced the smoothest surfaces. 2. Light curing microfilled composite resin, Silux, had smoother surface than any others. 3. The surfaces polished by Soflex were smoothest. 4. Aluminum oxide disk, Soflex and Super-Snap, made smoother surface than diamond bur, M.F.S., or silicon point, Composite polishing kit. 5. The roughness values of surface polished by M.F.S. composed of diamond burs, were less than those of Composite polishing kit made from silicone points.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.9
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• pp.737-740
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• 2009

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics, In this paper, we demonstrated that the switching performance of DMOSFETs are dependent on the with Channel length ($L_{channel}$) and Current Spreading Layer thickness ($T_{CSL}$) by using 2-D Mixed-mode simulations. The 4H-SiC DMOSFETs with a JFET region designed to block 800 V were optimized for minimum loss by adjusting the parameters of the JFET region, CSL, and epilayer. It is found that improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance. Therefore, accurate modeling of the operating conditions are essential for the optimizatin of superior switching performance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.95-96
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• 2005

나노 구조 제작을 위한 다양한 시도 중 블록 공중합체를 이용한 방법은 현재 활발한 연구가 진행되고 있는 분야이다. 본 연구에서는 비휘발성 메모리 소자의 용량 증가를 위하여 블록 공중합체 박막을 나노 마스크로 이용하고, 평행판헝 반응관 내에서 반응성 이온 에칭을 사용하여 나노 구조의 표면을 제작하였다. 에칭동안에 나노 마스크로서 사용할 블록 공중합체 박막은 PS-b-PMMA를 이용하여 제작하였고, UV를 주사하여 PMMA를 제거하고 수직적인 나노 흩을 구성하여 나노 패터닝이 가능하도록 하였다. 실험을 통하여 매우 균일한 나노 바늘 형태의 구조를 생성할 수 있으며, 반응기체와 유량의 조절을 통하여 다양한 표면 구조를 확인할 수 있었다. 블록 공중합체는 나노 마스크로서 뛰어난 기능을 나타내며, 이를 이용하여 나노 사이즈의 패터닝이 가능하고, 표면적 증가를 통하여 비휘발성 메모리 소자의 용량 증가에 기여할 수 있다.