• Journal of the Korean Crystal Growth and Crystal Technology
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• v.30 no.6
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• pp.271-276
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• 2020

In this study, an amorphous SiC block was manufactured using polycarbosilane (PCS), an organosilicon polymer. The dense SiC blocks were easily fabricated in various shapes via pyrolysis at 1100℃, 1200℃, 1300℃, 1400℃ after manufacturing a PCS molded body using cured PCS powder. Physical and chemical properties were analyzed using a thermogravimetric analyzer (TGA), scanning electron microscope (SEM), energy dispersive spectroscopy (EDS), and universal testing machine (UTM). The prepared SiC block was decomposed into SiO and CO gas as the temperature increased, and β-SiC crystal grains were grown in an amorphous structure. In addition, the density and flexural strength were the highest at 1.9038 g/㎤ and 6.189 MPa of SiC prepared at 1100℃. The manufactured amorphous silicon carbide block is expected to be applicable to other fields, such as the previously reported microwave assisted heating element.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.06a
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• pp.177-178
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• 2009

• Journal of Advanced Marine Engineering and Technology
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• v.21 no.3
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• pp.267-277
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• 1997

In this paper, heat conduction characteristics of the cylinder block of a small 3 - cylinder, 4¬stroke gasoline engine were analyzed using the 3 - dimensional finite element method. Based on the experimental data, the engine cycle simulation was carried out in order to obtain the heat transfer coefficient and the temperature of the gas and the mean heat transfer coefficient of the coolant. Heat transfer data of the gas, which were averaged with respect to exposure time to the wall, were taken as convective boundary conditions corresponding to the operating conditions to obtain the temperature fields of the block. Finally silicon nitride(Si3N4) was taken as the material of the block liner in order to investigate its temperature distribution characteristics and compare the results with the original ones.

• Journal of the Semiconductor & Display Technology
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• v.8 no.2
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• pp.31-35
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• 2009

In the silicon wafer polishing process, the mounting stage of silicon wafer on the ceramic carrier block has been using the polishing template which utilizes the porous surface instead of traditional wax mounting method. Here in this article, the experimental study is carried out in order to study the wafer demounting by water jet and the effects of operating conditions such as the water jet flowrate and the number of water jet nozzles on the wafer demounting time. It is found that the measured wafer demounting time is inversely proportional to the water flowrate per nozzle, regardless of number of nozzles used; implying that the stagnation pressure by the water jet impingement is the dominant key factor. Additionally, by using the transparent disk instead of wafer, the air bubble formation and growth is observed under the disk, making the passage of water flow, and subsequently demounting the wafer from the porous pad.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.88.1-88.1
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• 2012

Silicon nanowires (SiNWs), due to their unusual quantum-confinement effects that lead to superior electrical and optical properties compared to those of the bulk silicon, have been widely researched as a potential building block in a variety of novel electronic devices. The conventional means for the synthesis of SiNWs has been the vapor-liquid-solid method using chemical vapor deposition; however, this method is time consuming, environmentally unfriendly, and do not support vertical growth. As an alternate, the electroless etching method has been proposed, which uses metal catalysts contained in aqueous hydrofluoric acids (HF) for vertically etching the bulk silicon substrate. This new method can support large-area growth in a short time, and vertically aligned SiNWs with high aspect ratio can be readily synthesized with excellent reproducibility. Nonetheless, there still are rooms for improvement such as the poor surface characteristics that lead to degradation in electrical performance, and non-uniformity of the diameter and shapes of the synthesized SiNWs. Here, we report a facile method of SiNWs synthesis having uniform sizes, diameters, and shapes, which may be other than just cylindrical shapes using a modified nanosphere lithography technique. The diameters of the polystyrene nanospheres can be adjustable through varying the time of O2 plasma treatment, which serve as a mask template for metal deposition on a silicon substrate. After the removal of the nanospheres, SiNWs having the exact same shape as the mask are synthesized using wet etching technique in a solution of HF, hydrogen peroxide, and deionized water. Different electrical and optical characteristics were obtained according to the shapes and sizes of the SiNWs, which implies that they can serve specific purposes according to their types.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.189-189
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• 2015

Plasmonics, sensor, field effect transistors, solar cells 등 다양한 적용분야를 가지는 실리콘 구조체는 제작공정에 의해 전기적 및 광학적 특성이 달라지기 때문에 적합한 나노구조 제작방법이 요구되고 있다. 나노구조체 제작방법으로는 Photo lithography, Extreme ultraviolet lithography (EUV), Nano imprinting lithography (NIL), Block copolymer (BCP) 방식의 방법들이 연구되고 있으며, 특히 BCP는 direct self-assembly 특성을 가지고 있으며 가격적인 면에서도 큰 장점을 가진다. 하지만 BCP를 mask로 사용하여 식각공정을 진행할 경우 BCP가 버티지 못하고 변형되어 mask로서의 역할을 하지 못한다. 이러한 문제를 해결하기 위하여 본 논문에서는 BCP와 질화막을 이용한 double mask 방법을 사용하였다. 기판 위에 BCP를 self-assembly 시키고 mask로 사용하여 hole 부분으로 노출된 기판을 Ion gun을 통해 질화 시킨 후에 BCP를 제거한다. 기판 위에 hole 모양의 질화막 표면은 BCP와 다르게 etching 공정 중 변형되지 않는다. 이러한 질화막 표면을 mask로 사용하여 pillar pattern의 실리콘 나노구조체를 제작하였다. 질화막 mask로 사용되는 template은 PS와 PMMA로 구성된 BCP를 사용하였다. 140kg/mol의 polystyrene과 65kg/mol의 PMMA를 톨루엔으로 용해시키고 실리콘 표면 위에 spin coating으로 도포하였다. Spin coat 후 230도에서 40시간 동안 열처리를 진행하여 40nm의 직경을 가진 PS-b-PMMA self-assembled hole morphology를 형성하였다. 질화막 형성 및 etching을 위한 장비로 low-energy Ion beam system을 사용하였다. Reactive Ion beam은 ICP와 3-grid system으로 구성된 Ion gun으로부터 형성된다. Ion gun에 13.56 MHz의 frequency를 갖는 200W 전력을 인가하였다. Plasma로부터 나오는 Ion은 $2{\Phi}$의 직경의 hole을 가지는 3-grid hole로 추출된다. 10~70 voltage 범위의 전위를 plasma source 바로 아래의 1st gird에 인가하고, 플럭스 조절을 위해 -150V의 전위를 2nd grid에 인가한다. 그리고 3rd grid는 접지를 시켰다. chamber내의 질화 및 식각가스 공급은 2mTorr로 유지시켰다. 그리고 기판의 온도는 냉각칠러를 이용하여 -20도로 냉각을 진행하였다. 이와 같은 공정 결과로 100 nm 이상의 높이를 갖는 40 nm직경의 균일한 Silicon pillar pattern을 형성 할 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.23-29
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• 2010

This paper presents a method for constructing a memory system using defective memory chips comprising faulty storage blocks. The three-dimensional memory system introduced here employs a die-stacked structure of faulty memory chips. Signals lines passing through the through-silicon-vias (TSVs) connect chips in the defect tolerant structure. Defective chips are classified into several groups each group comprising defective chips having faulty blocks at the same location. A defect tolerant memory system is constructed using chips from different groups. Defect-free storage blocks from spare chips replace faulty blocks using additional routing circuitry. The number of spare chips for defect tolerance is $s={\ulcorner}(k{\times}n)/(m-k){\urcorner}$ to make a system defect tolerant for (n+s) chips with k faulty blocks among m independently addressable blocks.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.48-55
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• 2010

As the complexity and the clock speed of semiconductor integrated circuits increase, silicon validation becomes important. In this research, we developed new post-silicon repair & revision techniques to reduce cost and time-to-market. Spare cells are fabricated with the original design and are used for repair when necessary. The interconnections are modified by repair layer revision. The repair cost can be reduced by logic partitioning. Experimental results show that these techniques are effective for low-cost and fast turnaround repair.

• Journal of the Semiconductor & Display Technology
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• v.10 no.1
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• pp.1-6
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• 2011

In this paper, the air flow induced by the rotating flat disk is numerically investigated in a hope to better understand the air flow structures inside the wax spin coater for a silicon wafer polishing station. Due to the complex inner geometry of actual spin coater such as the casing around the rotating ceramic block and servo motor, recirculation of air flow is inevitably found on the coating target if the internal space of spin coater is closed at the bottom and it could be the possible source of contamination on the wax coating. By numerical flow simulation, we found that it is necessary to install the air vent at the bottom and to apply the sufficient air suction in order to control the path of air flow and to eliminate the air recirculation zone above the spinning surface of coating target.

• Proceedings of the Polymer Society of Korea Conference
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• 2006.10a
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• pp.311-311
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• 2006

The morphology of Poly(styrene-b-methylmethacrylate) (P(S-b-MMA)) block copolymer thin films deposited on silicon wafers was controlled by treating the substrates with Self-Assembled Monolayers (SAM) of phenylsilanes with different alkyl chain lengths. It was found that the treatment with SAM strongly modified the substrates properties, especillay the surface energy, as compared with bare silicon oxide. By futher adjusting the molecular weight of P(S-b-MMA), a variety of morphologies could be generated, including a perpendicular orientation of lamellea of PS and PMMA, which is required for industrial applications.