• Proceedings of the Materials Research Society of Korea Conference
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• 1997.05a
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• pp.12-12
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• 1997

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.128-128
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• 2012

We investigated the atomic and electronic properties of graphene grown by Pd silicidation and intercalation using LEED, STM, and ARPES. Pd was deposited on the 6H-SiC(0001) surface at RT. The formation of Pd silicide gives rise to breaking of Si-C bonds of the SiC crystal, which enables to release C atoms at low temperature. The C atoms are transformed into graphene from $860^{\circ}C$ according to the LEED patterns as a function of annealing temperature. Even though the graphene spots were observed in the LEED pattern and the Fourier transformed STM images after annealing at $870^{\circ}C$, the topography images showed various superstructures so that graphene is covered with Pd silicide residue. After annealing at $950^{\circ}C$, monolayer graphene was revealed at the surface. The growth of graphene is not limited by surface obstacles such as steps and defects. In addition, we observed that six protrusions consisting of the honeycomb network of graphene has same intensity meaning non-broken AB-symmetry of graphene. The ARPES results in the vicinity of K point showed the non-doped linear ${\pi}$ band structure indicating monolayer graphene decoupled from the SiC substrate electronically. Note that the charge neutrality of graphene grown by Pd silicidation and intercalation was sustained regardless of annealing temperature in contrast with quasi-free- standing graphene induced by H and Au intercalation. Further annealing above $1,000^{\circ}C$ accelerates sublimation of the Pd silicide layer underneath graphene. This results in appearance of the $(6r3x6r3)R30^{\circ}$ structure and dissolution of the ${\pi}$ bands for quasi-free-standing graphene.

• Korean Journal of Materials Research
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• v.10 no.2
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• pp.124-127
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• 2000

A new triode type Ti-silicided Si FEA(field emitter array) was realized by Ti-silicidation of Ti coated Si FEA and its field emission properties were investigated. In the fabricated device, the field emission properties through the unit pixel with $200{\mu\textrm{m}}{\times}200{$\mu\textrm{m}}$ tip array in the area of $1000{\mu\textrm{m}}{\times}1000{$\mu\textrm{m}}$ were as follows : the turn-on voltage was about 70V under high vacuum condition of $10^8Torr$, and the field emission current and steady state current degradation were about 2nA/tip and 0.3%/min under the bias of $V_A=500V\;and\;V_G=150V$. The low turn-on voltage and the high current stability during long term operation of the Ti silicided Si FEA were due to the thermal and chemical stability and the low work function of silicide layer formed at the surface of Si tip.

• Korean Journal of Materials Research
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• v.10 no.4
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• pp.301-304
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• 2000

A new triode type Co-silicided Si FEA(field emitter array) was realized by Co-silicidation of Co coated Si FEA and its field emission properties were investigated. The field emission properties of the fabricated device through the unit pixel with $45{\times}45$ tip array in the area of $250{\mu\textrm{m}}{\times}250{\mu\textrm{m}}$ under high vacuum condition of $10^{-8}Torr$ were as follows : the turn-on voltage was about 35V and the anode current was about $1.2\mu\textrm{A}(0.6㎁/tip)$ at the bias of $V_A=500V\;and\; V_G=55V$. The fabricated device showed the stable electrical characteristics without degradation of field emission current for the long term operation except for the initial transient state. The low turn-on voltage and the high current stability of the Co-silicided Si FEA were due to the thermal and chemical stability and the low work function of silicide layer formed at the surface of Si tip.

• Korean Journal of Materials Research
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• v.4 no.8
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• pp.855-860
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• 1994

Ta-silicide films in polycide structure were prepared by rapid thermal annealing of sputtered Ta film on poly-Si and doped poly-Si. Effects of phosphorus on Ta-silicide formation were investigated. Independent of the ion dose($1 \times 10^{13}\to 5 \times 10^{15}$/ions/$\textrm{cm}^2$), Ta-silicide phases were formed at $800^{\circ}C$ and stabilized above $1000^{\circ}C$. From the result of XRD at $800^{\circ}C$ and $900^{\circ}C$, however, it was indicated that the more the doping concentration the weaker the intensity of Ta-silicide phases. Furthermore, the observation of SEM revealed that the increase of the doping concentration retarded silicidation. As the temperature increased, the dopant effect was weakened gradually and almost disappeared at $1000^{\circ}C$. Therefore the variation of the ion dose from ($1 \times 10^{13}\to 5 \times 10^{15}$/ions/$\textrm{cm}^2$) did not greatly affect the formation of Ta-silicide at high temperatures but retarded slightly the silicidation at low temperatures.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.1
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• pp.25-32
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• 2007

We investigated the silicide reaction stability between 10 nm-Col-xNix alloy films and silicon substrates with the existence of 4 nm-thick natural oxide layers. We thermally evaporated 10 nm-Col-xNix alloy films by varying $x=0.1{\sim}0.9$ on naturally oxidized single crystal and 70 nm-thick polycrystalline silicon substrates. The films structures were annealed by rapid thermal annealing (RTA) from $600^{\circ}C$ to $1100^{\circ}C$ for 40 seconds with the purpose of silicidation. After the removal of residual metallic residue with sulfuric acid, the sheet resistance, microstructure, composition, and surface roughness were investigated using a four-point probe, a field emission scanning electron microscope, a field ion bean4 an X-ray diffractometer, and an Auger electron depth profiling spectroscope, respectively, to confirm the silicide reaction. The residual stress of silicon substrate was also analyzed using a micro-Raman spectrometer We report that the silicide reaction does not occur if natural oxides are present. Metallic oxide residues may be present on a polysilicon substrate at high silicidation temperatures. Huge residual stress is possible on a single crystal silicon substrate at high temperature, and these may result in micro-pinholes. Our results imply that the natural oxide layer removal process is of importance to ensure the successful completion of the silicide process with CoNi alloy films.

• Proceedings of the Materials Research Society of Korea Conference
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• 2002.11a
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• pp.108-108
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• 2002

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.607-610
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• 2005

In this paper, Ni Germanosilicide using Ni-Ta/Co/TiN is proposed to improve thermal stability. The sheet resistance of Ni Germanosilicide utilizing pure Ni increased dramatically after the post-silicidation annealing at $600^{\circ}C$ for 30min. However, using the proposed Ni-Ta/Co/TiN structure, low temperature silicidation and wide range of RTP process window were achieved.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.611-614
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• 2005

In this paper, investigated is the relationship between the formation temperature and the thermal stability of Ni silicide formed with Ni-V (Nickel Vanadium) alloy target. The sheet resistance after the formation of Ni silicide with the Ni-V showed stable characteristic up to RTP temperature of $700\;^{\circ}C$ while degradation of sheet resistance started at that temperature in case of pure-Ni. Moreover, the Ni silicide with Ni-V indicated more thermally stable characteristic after the post-silicidation annealing. It is further found that the thermal robustness of Ni silicide with Ni-V was highly dependent on the formation temperature. With the increased silicidation temperature (around $700\;^{\circ}C$), the more thermally stable Ni silicide was formed than that of low temperature case using the Ni-V.