• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.353-356
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• 2002

Due to the increased complexity and size of digital system and the need of the H/W-S/W co-design, C/C++ based system design methodology gains more Interests than ever in EDA field. This paper suggests the methodology in which handshake module corresponding to each basic statement of C is provided of the form of STG(Signal Transition Graph) and then, C statements is synthesized into asynchronous circuit through syntax-oriented translation. The 4-phase handshaking protocol is used for the communications between modules, and the modules are synthesized by the Petrify which is asynchronous logic synthesis CAD tool.

• Journal of the Korea Society for Simulation
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• v.10 no.1
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• pp.25-34
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• 2001

In this paper, we describe the generation method of interface logic which replace between IP & IP handshaking signal with asynchronous logic circuit. Especially, we suggest the new asynchronous sequential "Waveform to VHDL" code creation algorithm by flow chart conversion : Wave2VHDL - if only mixed asynchronous timing waveform is presented the level type input and pulse type input for handshaking, we convert waveform to flowchart and then replace with VHDL code according to converted flowchart. Also, we confirmed that asynchronous electronic circuits are created by applying extracted VHDL source code from suggest algorithm to conventional domestic/abroad CAD Tool, Finally, we assured the simulation result and the suggest timing diagram are identical.

• Proceedings of the KSR Conference
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• 1998.05a
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• pp.427-435
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• 1998

In this paper will be presented an algorithm for designing of a railway interlocking table which is a document describing the functional specification of the interlocking device. The ability to produce an interlocking table has been handed down in the signalling engineers society. And the signalling engineer makes the most of his expertise to produce an interlocking table. But, the expertise has not yet been organized into technical system, the core of the expertise is a hard nut to crack. Therefore, we analyze into signal engineering expertise, and propose a generalization of interlocking notion. Also, an algorithm is drawn up based on a train route setting principle to solve practical and general problems by computer And the performance of the algorithm is evaluated for test program based on AutoCAD technology. The evaluation result shows that it can be utilized as the effective algorithm for computer control of the signalling system as interlocking device, that it improved in safety

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1724-1727
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• 2002

Asynchronous circuits have the potential to solve the problems related to parameter variations such as gate delays in deep sub-micron technologies. However, current CAD tools for large-scale asyn-chronous circuits partition specification irrelevantly, because these tools cannot control the granularity of circuit decomposition. In this paper we propose a hierarchical Control/Data Flow Graph (CDFG) containing nodes that are flexibly partitioned or merged into other nodes. We show a partitioning algorithm for such CDFGs to generate handleable Signal Transition Graphs (STGs) for asynchronous synthesis tools. The algorithm a1lows designers to assign the maximum number of signals of partitioned nodes considering of timality. From an experiment, this algorithm can flexibly partition and result in more compact asynchronous controllers.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.5
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• pp.407-417
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• 2019

When a free-falling ballistic missile intercepts a maritime target in a sea clutter environment at high grazing angle, detection performance of the ballistic missile's seeker can be rapidly degraded by the effect of sea clutter. To solve this problem, it is necessary to verify the performance of maritime target detection via simulations based on various scenarios. We accomplish this by applying a two-dimensional cell -averaging constant false alarm rate detector to a two-dimensional radar image, which is generated by merging a sea clutter signal at high grazing angle with a maritime target signal corresponding to the signal-to-clutter ratio. Simulation results using a computer-aided design model and commercial numerical electromagnetic solver in various scenarios show that the performance of maritime target detection significantly depends on the grazing and azimuth angles.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.4
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• pp.173-179
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• 2002

This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. The DFE structure has better channel adaptive performance and lower BER than the transversal structure. The proposed equalizer can be used for 16/64 QAM modems. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL filter. The proposed equalizer shows low BER in multipath fading channel. We have performed models. From the simulation results, we employ a 12 tap feedback filter and a 8 tap feedforward logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5$\mu\textrm{m}$ standard cell library (STD80) and verified function and timing simulations. The total number of gates is about 130,000.

• Journal of the Society of Naval Architects of Korea
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• v.52 no.6
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• pp.452-459
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• 2015

It is important to use bench test results in the design process of anti-rolling tanks. Traditional bench tester is usually designed to perform only roll motions about a fixed axis and relatively small so that the viscous effects may not be neglected. Novel bench tester which could adjust the motion center to realize the coupled motion of sway and roll has been devised and manufactured therefore, large scaled bench tester could be utilized for designing the passive anti-rolling tanks. The time history of the reference signal from the rotation sensor of the bench tester have been recorded and processed to determine the phase angle to derive the Response Amplitude Operator(RAO) of the stabilized ship. The breadth of ART tank model should be large up to 2 m to diminish viscous scale effect and the vertical position of the tank can be varied with the ship's center of motion. The periods and the amplitude of roll motion can be varied from 1.5 sec to 5 sec and up to ±20°, respectively. The components of the tester was expressed in three dimensional digital mockup (DMU) and assembled together in the CAD space. The final configuration of the bench tester has been determined by confirming the smooth operation of the moving parts without interference through the animation in CAD space. New analytic logic are introduced for the determination of hydrodynamic moment and phase difference due to fluid motion in ART and verified through the test. The developed bench tester is believed to be effective and accurate for the verification of stabilization effect of ART taking into the consideration of the sway effect in the design stage.

• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.2
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• pp.409-416
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• 2024

With the expansion of floating-point operation requirements for fast high-speed data signal processing and logic operations, the speed of the floating-point operation unit is the key to affect system operation. This paper studies the performance characteristics of different floating-point multiplier schemes, completes partial product compression in the form of carry and sum, and then uses a carry look-ahead adder to obtain the result. Intel Quartus II CAD tool is used for describing Verilog HDL and evaluating performance results of the floating point multipliers. Floating point multipliers are analyzed and compared based on area, speed, and power consumption. The FMAX of modified Booth encoding with Wallace tree is 33.96 Mhz, which is 2.04 times faster than the booth encoding, 1.62 times faster than the modified booth encoding, 1.04 times faster than the booth encoding with wallace tree. Furthermore, compared to modified booth encoding, the area of modified booth encoding with wallace tree is reduced by 24.88%, and power consumption of that is reduced by 2.5%.

• Journal of the Korea Fashion and Costume Design Association
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• v.12 no.2
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• pp.119-129
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• 2010

오늘날 인간의 수명이 연장되고, 웰빙과 건강에 대한 관심이 증가됨에 따라서 언제 어디서나 건강을 모니터링 할 수 있는 건강 스마트 의류 시스템이 개발되고 있다. 이를 위하여 최근에는 생체신호의 모니터링이 가능하도록 디자인된 의류에 통합된 형태의 직물 전극이 개발되고 있다. 혁신적으로 의류 시스템에 통합되어 착용 가능한 니트, 우븐, 자수방식의 텍스타일 전극에 대한 다양한 연구가 개발 제시되고 있으며, 이의 일부는 상용화되어 있다. 이에 본 연구는 경위사의 일정한 직조제어 자동화 시스템이 가능한 컴퓨터 자카드 직기의 캐드(CAD) 직조디자인 방식을 통하여 생체신호 센싱 기능이 향상된 새로운 텍스타일 전극디자인을 연구하고자 하였다. 이를 위하여 본 연구에서는 기존 생체신호 센싱 전극의 개발 및 연구 동향, 비직물/전극 타입에 대한 단점과 장점에 대한 비교 분석을 이론적으로 살펴보고, 자카드 직조 직물 기반으로 심전도 센싱용 텍스타일 전극을 디자인하여 실험 연구하였다. 자카드 직조 방식의 심전도 센싱용 직물 전극은 전극 인터페이스 디자인 방식, 이중직물형 직조 디자인 방식, 사가공 등의 요인들을 고려하여 개발하였다. 본 연구에서 도출된 최종 자카드 직조 직물 기반의 텍스타일 전극은 스마트 의류에 통합시킨 텍스타일 전극 모듈로서 적용되여 향후 상용화 방안을 모색할 수 있다.

• Korean Journal of Computational Design and Engineering
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• v.2 no.3
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• pp.175-185
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• 1997

Given the widespread use of the Finite Element Method in strength analysis, automatic mesh generation is an important component in the computer-aided design of parts and assemblies. For a given resolution of geometric accuracy, the purpose of mesh generators is to discretize the continuous model of a part within this error limit. Sticking to this condition often produces many small elements around small features in spite that these regions are usually of little interest and computer resources are thus wasted. Therefore, it is desirable to selectively suppress small features from the model before discretization. This can be achieved by low-pass filtering a CAD model. A spatial function of one dimension higher than the model of interest is represented using the Fourier basis functions and the region where the function yields a value greater than a prescribed value is considered as the extent of a shape. Subsequently, the spatial function is low-pass filtered, yielding a shape without the small features. As an undesirable effect to this operation, all sharp corners are rounded. Preservation of sharp corners is important since stress concentrations might occur there. This is why the LPF (low-pass filtered) model can not be directly used. Instead, the distances of the boundary elements of the original shape from the LPF model are calculated and those that are far from the LPF model are identified and removed. It is shown that the number of mesh elements generated on the simplified model is much less than that of the original model.