• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• Journal of the Korea Institute of Military Science and Technology
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• v.19 no.5
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• pp.590-597
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• 2016

We designed the multiple scattering points generation system to simulate an actual situation of target signal for high range resolution radar system. This provides replicating the target signals and controlling the status of target signals for radar system. This is composed transmit antenna and multi target generator. Transmit antenna is waveguide array antenna and multi target generator has signal distribution module and control & power module. Multi target generator is able to provide the high isolation and variable output power. Moreover, in order to monitor all output signals of the multi target generator, the flows of signals are programed in control & power module. The performance is demonstrated using experimented results of high range resolution radar.

• Journal of IKEEE
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• v.20 no.3
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• pp.251-259
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• 2016

This paper describes that how to enhance the robustness of semiconductor TRM(Transmitter and Receiver Module) through the bias sequencing and tuning the switching time. Previous circuit designs focused on improving the MDS(Minimum Detection Signal) performance. Because TRM has critical problem which transmission output signal leak into receiver by it's compact design. Under this condition, TRM was frequently broken down within the MTBF(Mean Time Between Failure). This study proposes the bias sequencing and tuning the switching time to improve above problem. At first, we collected major failure symptom and infer it's cause. Second, we demonstrated it's effect by derive the improvement method and apply it to our system. And finally we can convinced that the proposed method clear the frequent failure problem with its lack of isolation.

• Journal of Sensor Science and Technology
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• v.32 no.5
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• pp.320-327
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• 2023

In this study, an FPGA-based sealer inspection system was developed to inspect the sealer applied to install vehicle glass on a car body. The sealer is a liquid or paste-like material that promotes adhesion such as sealing and waterproofing for mounting and assembling vehicle parts to a car body. The system installed in the existing vehicle design parts line does not detect the sealer in the glass rotation section and takes a long time to process. This study developed a line laser camera sensor and an FPGA vision signal processing module to solve this problem. The line laser camera sensor was developed such that the resolution and speed of the camera for data acquisition could be modified according to the irradiation angle of the laser. Furthermore, it was developed considering the mountability of the entire system to prevent interference with the sealer ejection machine. In addition, a vision signal processing module was developed using the Zynq-7020 FPGA chip to improve the processing speed of the algorithm that converted the profile to the sealer shape image acquired from a 2D camera and calculated the width and height of the sealer using the converted profile. The performance of the developed sealer application inspection system was verified by establishing an experimental environment identical to that of an actual automobile production line. The experimental results confirmed the performance of the sealer application inspection at a level that satisfied the requirements of automotive field standards.

• Aerospace Engineering and Technology
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• v.11 no.2
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• pp.1-11
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• 2012

This paper describes the transmit/receive(T/R) module for the space based X-band active phased array radar. T/R module is the integrated module which is assembled by the transmitting and receiving RF semiconductor devices to enable the electronically beam steering of the phased array antenna and the key component of the SAR payload. T/R module can selectively receive the polarization signals by the switch according to the established technology but now the technological trend of the T/R module is to receive the horizontal and vertical polarization signal simultaneously. Therefore the research and development of the dual polarization receiving channel T/R module is actively in progress. In this study, as the prior research for the next generation SAR payload, the technological trend of the active phased array radar T/R module and the result of the preliminary design of the dual receiving channel T/R module were described.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.20 no.2
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• pp.15-29
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• 2021

The signal intersection is the most challenging space for autonomous vehicles. To promote the safe driving of autonomous vehicles on urban roads with traffic signals, autonomous vehicles need to receive traffic signal information from infrastructure through V2I communication. Thus, a protocol for providing traffic signal information was added to the standard traffic signal controller specification of the National Police Agency. On the other hand, there are technical limitations when applying this to digital traffic signal controllers because the protocols are defined mainly for analog traffic signal controllers. Therefore, this study proposes developing a signal information linkage module to provide traffic signal information from a digital traffic signal controller to an autonomous vehicle and an algorithm improvement method that can provide accurate traffic signal information at the time of traffic signal transition.

• Journal of Navigation and Port Research
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• v.29 no.1 s.97
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• pp.91-96
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• 2005

The National Marine Electronics Association(NMEA) is nonprofit-making cooperation composed with manufacturers, distributors, wholesalers and educational institutions. We use the basic port of equipment in order to process the signal from NMEA signal using equipment. When we don't have enough one, we use the multi-port for processing. However, we need to have module development simulation which could multiplex and provide NMEA related signal that we could solve the problems in multi-port application and exclusive equipment generation for a number of signal. For now, we don't have any case or product using NMEA multiplexer so that we import expensive foreign equipment or embody NMEA signal transmission program like software, using multi-port. These have problems since we have to pay lots ci money and build separate processing part for every application programs. Besides, every equipment generating NMEA signal are from different manufactures and have different platform so that it could cause double waste and loss of recourse. For making up for it, I suggest the NMEA multiplexer embodiment, which could independently move by reliable process and high performance single hardware module, improve the memory efficiency of module by designing the optimized Queue, and keep having reliability for realtime communication among the equipment such as main input sensor equipment Gyrocompass, Echo-sound, and GPS.

• Journal of the Institute of Convergence Signal Processing
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• v.16 no.4
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• pp.162-167
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• 2015

This paper describes the reason and the problem solving for the double-layer pattern of a Daejeon correlator operated in Korea-Japan Correlation Center. When the electric power of an input signal in the correlator is charged small enough to be buried in the noise, it is hard to see a signal with a specific pattern in the input signal, but when the electric power is large, a specific one is reported to be seen. By comparing data from observation with one from software correlator, it was confirmed from the analysis using the AIPS software that the amplitude gain of a source signal was affected about 3%. Therefore, in order to solve the problem of double-layer patterns, we found that a problem in the memory management module responsible for both the data input and the data serialization of the correlator is a cause for the double-layer pattern detected periodically. In other words, while data is serialized and read repeatedly in the memory area assigned to serialize the data from the serialization module, redundant last data is generated and an overlap for the memory allocation is occurred. Therefore, by modifying the program of the FPGA memory sections on serialization module to correct the problem, we confirmed that double-layer pattern is disappeared and correlation results are normally acquired.

• Journal of Positioning, Navigation, and Timing
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• v.9 no.4
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• pp.337-345
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• 2020

In this paper, an efficient signal tracking method to simultaneously track both GPS L1 C/A and Galileo E1B CBOC(6,1,1/11) using a low cost GPU is proposed. In the existing method that each GNSS signal is processed within 1 ms, more than 2 ms processing time is required in GPU to process 4 ms CBOC signal. It means that real time operation is possible if only Galileo E1B CBOC signal is concerned. But when both GPS C/A and Galileo CBOC is required, it cannot process GPS C/A signal in real time. To process 1 ms GPS C/A and 4 ms Galileo CBOC signal in real time, 4 ms Galileo CBOC signal is divided into 4 by 1 ms signal block in the proposed method. Specially, a buffer that simultaneously manages 1 ms and 4 ms signals is designed. In addition, a module that accumulates the 1 ms correlation value of the Galileo CBOC by 4 ms and passes it to the PLL and DLL is implemented. The operation and performance are evaluated with real measurements in the GPU based SDR. The experimental results show that tracking of more than 16 satellites of GPS C/A and Galileo E1B is possible using the proposed method.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.10a
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• pp.293-316
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• 2006

[ $\blacksquare$ ] I/O Signal $\square$ We see adequate margin for the RC B design $\square$ Minimum ODW value is 328ps using Ac to DC measurement for the read case. $\square$ Minimum ODW value is 350ps using AC to DC mesurement method for the write case. $\blacksquare$ CLK Signal $\square$ The slew-rate decreases when the Cterm value increases $\square$ Lower slew-rate could effect delay and jitter. $\square$ There are some ldge issues during transitions with lower Cterm and without Cterm. $\square$ Our recommendation for the Cterm value range is between 1.5pF to 2.4pF. $\blacksquare$ ADD/CMD/Ctrl Signal $\square$ High output slew-rate at low VDD causes ring back that reduces voltage margin because of x-talk. $\square$ 30ohm Rterm for the CTRL signal shows a better signal integrity result compared to 36ohm.