• Journal of IKEEE
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• v.21 no.4
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• pp.331-337
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• 2017

In this paper, we present the design of a 20MHz bandwidth 3rd-order continuous-time low-pass sigma-delta modulator with low-noise and low-power consumption. The bandwidth of the system is sufficient to accommodate LTE and other wireless network standards. The 3rd-order low-pass filter with feed-forward architecture achieves the low-power consumption as well as the low complexity. The system uses 3bit flash quantizer to provide fast data conversion. The current-steering DAC achieves low-power and improved sensitivity without additional circuitries. Cross-coupled transistors are adopted to reduce the current glitches. The proposed system achieves a peak SNDR of 65.9dB with 20MHz bandwidth and power consumption of 32.65mW. The in-band IM3 is simulated to be 69dBc with 600mVp-p two tone input tones. The circuit is designed in a 0.18-um CMOS technology and is driven by 500MHz sampling rate signal.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.1
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• pp.9-15
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• 2015

A CMOS band-pass delta-sigma modulator(BPDSM) and cascode class-E power amplifier have been developed CMOS for Class-S power amplifier applications. The BPDSM is operating at 1-GHz sampling frequency, which converts a 250-MHz sinusoidal signal to a pulse-width modulated digital signal without the quantization noise. The BPDSM shows a 25-dB SQNR(Signal to Quantization Noise Ratio) and consumes a power of 24 mW at an 1.2-V supply voltage. The class-E power amplifier exhibits an 18.1 dBm of the maximum output power with a 25% drain efficiency at a 3.3-V supply voltage. The BPDSM and class-E PA were fabricated in the Dongbu's 110-nm CMOS process.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.5
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• pp.531-537
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• 2018

A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.

• Korean Journal of Optics and Photonics
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• v.7 no.2
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• pp.89-95
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• 1996

Superresolution optics, employing Gaussian apodization, is rigorously treated at the soft X-ray wave-length(λ=0.013 ${\mu}{\textrm}{m}$) region. In the diffraction integral, the line integral along the imaginary axis is found small, and it is ignored, so that the diffraction integral consists of the integration along the real axis. The resolution of the diffracted image is not effected by the pupil angular frequency bandwidth $2{\omega}_0$, which is one of the most important the characteristic features of Gaussian apodization ($e^{-o^2x^2}$ optics. The superresolution optics has resolution ($\frac{1}{2}{\times}FWHM)$=$\Delta$x=0.008 $\mu$m which is smaller than the Rayleigh criterion of 2λ=0.026 ${\mu}{\textrm}{m}$ for NA=0.25. The optical system has ${\omega}_0{\ge}\frac{1}{2}{\sigma}$, which gives the peak intensity of the diffracted image larger than $e^{-2}$ times intensity obtainable by the infinite sperture.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.651-657
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• 2018

A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1619-1626
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• 2021

Unlike traditional delta-sigma analog-to-digital converters, incremental analog-to-digital converters enable 1:1 mapping of input and output through a reset operation, which can be used very easily for multiplexing. Incremental analog-to-digital converters also allow for simpler digital filter designs compared to traditional delta-sigma converters. Therefore, starting with analysis in the time domain of the delayed integrator and non-delayed integrator, which are the basic blocks of analog-to-digital converter design, the design equations of a second-order input feed-forward, extended counting, 2+1 MASH (Multi-stAge-noise-SHaping), 2+2 MASH incremental analog-to-digital converter are derived in this paper. This allows not only prediction of the performance of the incremental analog-to-digital converter before design, but also the design of a digital filter suitable for each analog-to-digital converter. In addition, extended counting and MASH design techniques were proposed to improve the accuracy of analog-to-digital converters.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.5
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• pp.335-342
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• 2022

In this paper, a single-bit 3rd-order feedforward delta sigma modulator is proposed for audio applications. The proposed modulator is based on a class-C inverter for low voltage and power applications. For the high-precision requirement, the class-C inverter with regulated cascode structure increases its DC gain and acts as a low-voltage subthreshold amplifier. The proposed Class-C inverter-based modulator is designed and simulated in 180-nm CMOS process. With no performance loss and a low supply voltage compatibility, the proposed class-C inverter-based switched-capacitor modulator achieves high power efficiency. This design achieves an signal-to-noise-and-distortion ratio (SNDR) of 93.9 dB, an signal-to-noise ratio (SNR) of 108 dB, an spurious-free dynamic range (SFDR) of 102 dB, and a dynamic range (DR) of 102 dB at a signal bandwidth of 20 kHz and a sampling frequency of 4 MHz, while only using 280 μW of power consumption from a 0.8-V power supply.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.7
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• pp.4398-4404
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• 2015

Stainless steel sheets are widely used as the structural material for dynamic machine structures, These kinds structures used stainless steel sheets are commonly fabricated by using the gas welding, For fatigue design of gas welded joints such as various type joint. It is necessary to obtain design information on stress distribution at the weldment as well as fatigue strength of gas welded joints. Thus in this paper, ${\Delta}P-N_f$ curves were obtained by fatigue tests. and, ${\Delta}P-N_f$ curves were rearranged in the ${\Delta}{\sigma}-N_f$ relation with the hot spot stresses at the gas welded joints. Using these results, the accelerated life test(ALT) is conducted. From the experiment results, an life prediction model is derived and factors are estimated. So it is intended to obtain the useful information for the fatigue lifetime of welded joints and data analysis by statistic reliability method, to save time and cost, and to develop optimum accelerated life prediction plans.

• Korean Journal of Optics and Photonics
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• v.7 no.4
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• pp.434-439
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• 1996

To investigate influence of the incident beams which have the truncated Gaussian amplitude and of the shapes of bump on read-out signal is an optical disc, and the point spread function on bump, the scalar diffraction theory is used in this paper. We consider the truncated Gaussian amplitudes which are $\sigma$=0, 0.5, 1.5, and 2.5, the height of bump which is given by $n{\Delta}_0={\lambda}/4$, and the phase height of bump which is then given by ${\Phi}_0={\pi}$. We also consider the shapes of the bump which are a rectangular shape, a frustoconical shape, and a conical shape. It is shown that as the truncation of incident beam reduces the radius of central spot on bump decreases, the maximum value of read-out signal increases, and that the size of bump decreases. From these results, we get better read-out signal and the reduced cross-talk in optical disc when the truncation of incident beam reduces. Therefore a laser beam having less truncated Gaussian amplitude may useful for an actual optical disc.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.75-82
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• 2010

This paper presents a wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer for a multi-band single chip CMOS RFIC transceivers. A wideband VCO utilizes a 6-bit switched capacitor array bank for 2340~3940 MHz frequency range. VCO frequency calibration circuit is designed for optimal capacitor bank code selection before phase locking process. It finishes the calibration process in $2{\mu}s$ over the whole frequency band. The LO generation block has selectable multiple division ratios of ${\div}2$, ${\div}16$, and ${\div}32$ to generate LO I/Q signals for T-DMB/DAB/FM Radio systems in L-Band (1173~1973 MHz), VHF-III (147~246 MHz), VFH-II (74~123 MHz), respectively. The measured integrated phase noise is quite low as it is lower than 0.8 degree RMS over the whole frequency band. Total locking time of the ${\Delta}{\Sigma}$ frequency synthesizer including VCO frequency calibration time is less than $50{\mu}s$. The wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer is fabricated in $0.13{\mu}m$ CMOS technology, and it consumes 15.8 mA from 1.2 V DC supply.