• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.598-599
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• 2017

In motor application, High efficiency is important. So Design engineer select small gate resistor for lower switching. But There is side effect with small gate resistor. It makes large dv/dt and system request large EMI filter. It makes price increase. This paper introduce about gate drive IC which have solution both of lower loss and EMI issue.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.2
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• pp.120-126
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• 2006

A gate driver with Boot-strap chain is proposed to drive Multi-level PDP sustain switches. The proposed gate driver uses only one boot-strap capacitor and one diode per each MOSFETs switch without floating power supply. By adoption of this gate driver circuits, the size, weight and the cost of the driver board can be reduced.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.8
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• pp.651-657
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• 2000

The notching effect in etching of undoped amorphous silicon gate had different characteristics and mechanism comparing with reported ones. The undoped amorphous silicon was etched by using HBr gas plasma. First in the region of small line width the potential increased as a result of ions in the exposed surface of oxide and the incident ions between the small line widths were deflected more wide range therefore the depth of notching was shallow and wide. Second in the region of large line width of gate electrons were charged on the top of photoresist and the side of gate a part of ions deflected. The deflected ions were partly charged positive on the side of gate and then these partly charged ions produced potential difference. Therefore ions stored up more at independent line than at dense line and notching became deeper by Br ion bombardments.

• Macromolecular Research
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• v.17 no.9
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• pp.646-650
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• 2009

We report the fabrication of pentacene organic field-effect transistors (OFETs) using a fluorinated styrene-alt-maleic anhydride copolymer gate dielectric, which was prepared from styrene derivatives with a fluorinated side chain [$-CH_2-O-(CH_2)_2-(CF_2)_5CF_3$] and maleic anhydride through a solution polymerization technique. The fluorinated side chain was used to impart hydrophobicity to the surface of the gate dielectric and maleic anhydride was employed to improve its wetting properties. A field-effect mobility of 0.12 cm$^2$/Vs was obtained from the as-prepared top-contact pentacene FETs. Since various functional groups can be introduced into the copolymer due to the nature of maleic anhydride, its physical properties can be manipulated easily. Using this type of copolymer, the performance of organic FETs can be enhanced through optimization of the interfacial properties between the gate dielectric and organic semiconductor.

• Journal of Korea Water Resources Association
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• v.51 no.7
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• pp.555-564
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• 2018

The detention reservoir is a hydraulic structure that constructs a levee on the inland of river and sets up side weir in a section of the levee, and this facility stores a part of the flood volume in case of a flood event over a certain scale. In order to optimize the operation of detention reservoir, it is necessary to review the linkage with existing facilities in the river. In this study, the effect of water level reduction and the flow distribution was analyzed according to the location of the side weir in the detention reservoir considering the run-of-the-river gate. Two radial gates were installed in the experimental channel, and the water level in channel and the overflow of weir were measured by moving the location of the side weir upstream from the gate. As a results of experiment, it was confirmed that the water level reduction is more remarkable as the location of the side weir was closer to the gate, and the effect of flow distribution is not greatly changed. When two or more side weirs were operated, it is confirmed that the sufficient storage space was secured and the water level reduction effect with the location of the side weir is not large. In addition, the water level reduction rate according to the location of the side weir was estimated by empirical formula and it is provided as basic data that can be used in the planning of the detention reservoir.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.230-238
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• 2017

We have proposed an InGaAs-based gate-all-around (GAA) tunneling field-effect transistor (TFET) with a stacked dual-metal gate (DMG). The electrical performances of the proposed TFET are evaluated through technology computer-aided design (TCAD) simulations. The simulation results show that the proposed TFET demonstrates improved DC performances including high on-state current ($I_{on}$) and steep subthreshold swing (S), in comparison with a single-metal gate (SMG) TFET with higher gate metal workfunction, as it has a thinner source-channel tunneling barrier width by low workfunction of source-side channel gate. The effects of the gate workfunction on $I_{on}$, the off-state current ($I_{off}$), and S in the DMG-TFETs are examined. The DMG-TFETs with PNPN structure demonstrate outstanding DC performances and RF characteristics with a higher n-type doping concentration in the $In_{0.8}Ga_{0.2}As$ source-side channel region.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.487-490
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• 2006

We propose a new method to achieve well-defined surface properties of the polymeric gate dielectrics without using SAM technique and inserting another organic/inorganic buffer layer. Pentacene thin film transistors(OTFTs) fabricated with the polyimide gate insulators with different side chain structures were demonstrated. Further, a relationship between the surface properties (surface morphology, surface energy, etc) of the films and the performance of OTFTs have investigated, which will be given in more detail in presentation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.17-24
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• 2004

Quantum effects in the poly-gate are analyzed in two dimensions using the density-gradient method, and their impact on the short-channel effect of double-gate MOSFETs is investigated. The 2-D effects of quantum mechanical depletion at the gate to sidewall oxide is identified as the cause of large charge-dipole formation at the corner of the gate. The bias dependence of the charge dipole shows that the magnitude of the dipole peak-value increases in the subthreshold region and there is a large difference in carrier and potential distribution compared to the classical solution. Using evanescent-nude analysis, it is found that the quantum effect in the poly-gate substantially increases the short-channel effect and it is more significant than the quantum effect in the Si film. The penetration of potential contours into the poly-gate due to the dipole formation at the drain side of the gate corner is identified as the reason for the substantial increase in short-channel effects.

• Journal of Soil and Groundwater Environment
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• v.28 no.3
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• pp.1-11
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• 2023

Permeable reactive barrier (PRB) is a prominent in-situ remedial option for cleanup of contaminated groundwater and has been gaining increasing popularity in recent years. Funnel-and-gate systems, comprised of two side wings of impermeable walls and a central gate wall, are frequently implemented in many sites, but often suffers from bypassing of groundwater due to the progressive clogging of the gate wall over extended period of time. This study investigated technical feasibility of a hybrid funnel-and-gate system designed to address the flow deterioration in the gate wall. The key attribute of the proposed hybrid system is the operation of drainage units at the barrier walls and rear end of the gate wall. A conceptual modeling with MODFLOW indicated the groundwater inside the barrier was maintained at appropriate level to be guided toward the gate wall, yielding constant discharging of groundwater from the gate.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.2
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• pp.485-490
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• 2010

We propose the equivalent circuit model including all parasitic components in input gate of sense amplifier of DDI DRAM with butting contact structure. We analysed the effect of parasitic schottky diode by using the proposed model in the operation of sense amplifier. The cause of single side fail and the temperature dependence of fail rate in DDI DRAM are due to creation of the parasitic schottky diode in input gate of sense amplifier. The parasitic schottky diode cause the voltage drop in input gate, and result in decreasing noise margin of sense amplifier. therefore single side fail rate increase.