• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.489-492
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• 1999

The effects of alternate bias stress on p-channel poly-Si TPT's has been systematically investigated. It has been shown that the application of alternate bias stress affects device degradation for the negative bias stress as well as device improvement for the positive bias stress. This effects have been related to the hot carrier injection into the gate oxide rather than the generation of defect states within the poly-Si/SiO$_2$ under bias stress.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.62.2-62.2
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• 2010

박막 실리콘 태양 전지는 저가격화 및 대량생산, 대면적화에 유리하다는 장점을 가지고 있다. 단점으로 지적되는 낮은 효율을 극복하기 위해 광흡수층의 밴드갭이 서로 다른 두 개 이상의 박막을 적층하여, 넓은 파장 대역의 빛을 효과적으로 흡수함으로써 광변환 효율을 올리기 위한 많은 연구가 이루어지고 있다. 서로 다른 밴드갭의 광흡수층을 가진 p-i-n 구조를 다중 적층하여 고효율의 태양 전지를 제작하기 위해서는 n-도핑층과, p-도핑층 간에 전자와 정공이 빠르게 재결합할 수 있는 터널 접합(Tunnel Recombination Junction)의 형성이 필수적이며, 이때 광손실이 최소화되도록 해야한다. 만약 터널 접합이 적절하게 형성되지 않으면 결합되지 않은 전자와 정공이 도핑층 사이에 쌓이게 되고, 도핑층 사이의 저항 증가로 태양 전지의 광변환 효율은 크게 하락한다. 이번 연구에서는 터널 접합이 잘 이루어지게 하기 위한 n-도핑층 및 p-도핑층 박막의 특성과, 터널 접합의 특성에 따른 적층형 태양 전지의 광효율 변화를 확인하였다. 광흡수층 및 도핑층은 TCO($SnO_2:F$, Asahi) 유리 기판 위에 PECVD를 사용하여 p-i-n 구조로 RF Power 조건에서 증착되었고, ${\mu}c$-Si 광흡수층의 경우에는 VHF Power 조건에서 증착되었다. 광흡수층이 a-Si/${\mu}c$-Si의 구조를 가지는 이중 접합 태양 전지에서 ${\mu}c$-Si n-도핑층/${\mu}c$-Si p-도핑층 사이의 터널 접합 실험 결과 n-도핑층 및 p-도핑층의 결정화도와 도핑 농도를 조절하여 터널 접합의 저항을 최소화했고, 터널 접합 특성이 이중 접합 셀의 광효율 특성과 유사한 경향을 보임을 확인하였다. 광흡수층이 a-Si/a-SiGe/${\mu}c$-Si의 구조를 가지는 삼중 접합 태양 전지 실험의 경우 a-Si과 a-SiGe 광흡수층 사이에 ${\mu}c$-Si n-도핑층/${\mu}c$-Si p-도핑층/a-SiC p-도핑층의 구조를 적용하여 터널 접합을 형성하였으며, ${\mu}c$-Si p-도핑층의 두께 및 박막 특성을 개선하여 광손실이 최소화된 터널 접합을 구현하였고, 삼중 접합 태양 전지에 적용되었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.11
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• pp.910-917
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• 2009

We have designed a new structures of Junction Field Effect Transistor(JFET) using SILVACO simulation to improve electrical properties and process reliability. The device structure and process conditions of Si control JFET(Si JFET) were determined to set cut off voltage and drain current(at Vg=0 V) to -0.46 V and $300\;{\mu}A$, respectively. Among many design parameters influencing the performance of the device, the drive-in time of p-type gate is presented most predominant effects. Therefore we newly designed SiGe JFET, in which SiGe layers were placed above and underneath of Si-channel. The presence of SiGe layer could lessen Boron into the n-type Si channel, so that it would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer could be explained in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.

• Journal of Korea Foundry Society
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• v.15 no.6
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• pp.574-587
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• 1995

The $SiC_p-reinforced$ preforms fabricated by spray casting process were hot-extruded and subsequently T6-treated, and the morphology of the silicon phase and the grain size for these preforms and extruded samples were examined by Image Analyzer. Experimental observation revealed that with increase in volume percent of SiC particles, the grain size and silicon phase of the $Al-Si/SiC_p$ composites become finer, the shape of Si phase is changed from blocky to granular type, and aspect ratio of Si phase tend to become unity. Wear-tests with various sliding velocities, show that the wear resistance of spray cast specimen is increased remarkably compare to the permanent mold cast specimen at the sliding velocity range of $1.98{\sim}2.38m/sec$.. Microstructural observations for the worn surfaces of specimens revealed that wear resistance of Al-Si alloys at certain sliding velocities could be improved not only by the fine grain size of aluminum matrix but also the fine size and granular shape of silicon phases. The wear resistance of $SiC_p$ reinforced aluminum composites was found to be sensitive to the volume percentage of the reinforcing particles. The worn surfaces with various sliding velocities, show that change in wear mechanism seems to occur at the sliding velocity of near 2m/sec for all samples, and such a change in mechanism is delayed with increase in $SiC_p$ volume fraction.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.11 no.1
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• pp.38-42
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• 2001

Electric and dielectric(Ba,Sr)$TiO_3$[BST] thin films for emtal-Insulator-Semiconductor(MIS) capacitors have been studied. BST thin films wre deposted on p-Si(100) substrates bythe RF magnetron sputtering with tempratue range of 500~$600^{\circ}C$. The dielectric properties of MIS capacitors consisting of Al/BST/$SiO_2$/Si sandwich structure were evaluated ot redcue the leakage current density. The charge state densities of the MIS capacitors were determined by high frequency (1 MHz) C-V measurement. In order to reduce the leakage current in MIS capacitor, high quality $SiO_2$ layer was deposited on bare p-Si substrate. Depending on the oxygen pressure and substrate temperature both positive and negative polarities of effective oxide charge in the MIS capacitors were evaluated. It is considered that the density of electronic states, generated at the BST/$SiO_2$/p-Si interface due to the asymmetric structure within BST/$SiO_2$/Si structure, and the oxygen vacancy content has influence on the behavior of oxide charge.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1449-1450
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• 2011

The SiC-$ZrB_2$ composites were produced by subjecting a 40:60 (vol.%) mixture of zirconium diboride($ZrB_2$) powder and ${\beta}$-silicon carbide (SiC) matrix to spark plasma sintering(SPS) under argon atmosphere at 50MPa(P50) and 60MPa(P60) pressure. The relative density, 94.13% of P60 sample was lower than that, 94.75% of P50 sample. Reactions between ${\beta}$-SiC and $ZrB_2$ were not observed via x-ray diffraction (hereafter, XRD) analysis. The trend of flexural strength of SiC-$ZrB_2$ composites were in accordance with the relative density. The properties of a SiC-$ZrB_2$ composites through SPS under argon atmosphere were positive temperature coefficient resistance in the temperature range from $25^{\circ}C$ to $500^{\circ}C$, and electrical resistivity of P50 and P60 sample were $6.75{\times}10^{-4}$ and $7.22{\times}10^{-4}{\Omega}{\cdot}cm$ at room temperature, respectively.

• 한국신재생에너지학회:학술대회논문집
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• 2011.11a
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• pp.64.2-64.2
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• 2011

a-Si 박막 태양전지는 a-Si:H을 유리 기판 사이에 주입해 만드는 태양전지로, 뛰어난 적용성과 경제성을 지녔으나 c-Si 태양전지에 비해 낮은 변환 효율을 보이는 단점이 있다. 변환 효율을 높이기 위한 연구 방법으로는 a-Si 박막 태양전지 단일cell 제작 시 high Bandgap을 가지는 p-layer를 사용함으로 높은 Voc와 Jsc의 향상에 기여할 수 있는데, 이 때 p-layer의 defect 증가와 activation energy 증가도 동시에 일어나 변환 효율의 증가폭을 감소시킨다. 이를 보완하기 위해 본 실험에서는 p-layer에 기존의 p-a-Si:H를 사용함과 동시에 high Bandgap의 buffer layer를 p-layer와 i-layer 사이에 삽입함으로써 그 장점을 유지하고 높은 defect과 낮은 activation energy의 영향을 최소화하였다. ASA 시뮬레이션을 통해 a-Si:H보다 high Bandgap을 가지는 a-SiOx 박막을 사용하여 p-type buffer layer의 두께를 2nm, Bandgap 2.0eV, activation energy를 0.55eV로 설정하고, i-type buffer layer의 두께를 2nm, Bandgap 1.8eV로 설정하여 삽입하였을 때 박막 태양전지의 변환 효율 10.74%를 달성할 수 있었다. (Voc=904mV, Jsc=$17.48mA/cm^2$, FF=67.97).

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.385-385
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• 2012

A two terminal N+/P/N+ junction device to replace the conventional selective transistor was studied as a bilateral switching device for spin transfer torque (STT) MRAM based on 3D device simulation. An N+/P/N+ junction structure with $30{\times}30nm$ area requires bi-directional current flow enough to write a data by a drain induced barrier lowering (DIBL) under a reverse bias at N+/P (or P/N+ junction), and high current on/off ratio of 106. The SiGe materials are widely used in hetero-junction bipolar transistors, bipolar compensation metal-oxide semiconductors (BiCMOS) since the band gap of SiGe materials can be controlled by changing the fraction and the strain epilayers, and the drift mobility is increased with the increasing Ge content. In this work, N+/P/N+ SiGe material based junction provides that drive current is increased from 40 to $130{\mu}A$ by increased Ge content from 10~80%. When Ge content is about 20%, the drive current density of SiGe device substantially increased to 2~3 times better than Si-based junction device in case of 28 nm P length, which is sufficient current to operation of STT-MRAM.

• Korean Journal of Materials Research
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• v.15 no.5
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• pp.318-322
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• 2005

Ti-capped NiSi contacts were formed on $p^+/n$ junctions to improve the leakage problem and then Cu was deposited without removing the Ti-capping layer in an attempt to utilize as a diffusion barrier. The electrical characteristics of these $p^+/n$ diodes with Cu/Ti/NiSi electrodes were measured as a function of drive-in RTA(rapid-thermal annealing) and silicidation temperature and time. When drive-in annealed at $900^{\circ}C$, 10 sec. and silicided at $500^{\circ}C$, 100 sec., the diodes showed the most excellent I-V characteristics. Especially, the leakage current was $10^{-10}A$, much lower than reported data for diodes with NiSi contacts. However, when the $p^+/n$ diodes with Cu/Ti/NiSi contacts were furnace-annealed at $400^{\circ}C$ for 40 min., the leakage current increased by 4 orders. The FESEM and AES analysis revealed that the Ti-capping layer effectively prohibited the Cu diffusion, but was ineffective against the NiSi dissociation and consequent Ni diffusion.

• 한국신재생에너지학회:학술대회논문집
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• 2007.11a
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• pp.275-277
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• 2007

유리를 기판으로 하는 superstrate pin 비정질 태양전지에서 전면투명전도막(TCO)과 p-layer의 계면이 태양전지의 효율을 내는데 가장 큰 기여를 한다. 전면투명전도막(TCO)으로 현재 일반적으로 사용되는 ZnO:Al는 $SnO_2:F$ 보다 전기,광학적으로 우수하고, 안개율(Haze)높으며, 수소 플라즈마에서의 안정성이 높은 특정을 갖고 있다. 그래서 박막 태양전지 특성향상에 매우 유리하나, 태양전지로 제조했을 때, $SnO_2:F$보다 충진율(Fill factor:F.F)과 V_{\infty}$ 가 감소한다는 단점을 가지고 있다. 본 실험실에서는 $SnO_2:F$의 F.F가 72%이 나온 반면 ZnO:Al의 F.F은 68%에 그쳤다. 이들 원인을 분석하기 위해 TCO/p-layer의 전기적 특성을 알아 본 결과, $SnO_2:F$보다 ZnO:Al의 직렬저항이 높게 측정되었다. 이러한 결과를 바탕으로 p-layer 에 R={$H_2/SiH_4$}=25로 변화, p ${\mu$}c$-Si:H/p a-SiC:H 로 p-layer 이중 증착, p-layer의 boron doping 농도를 증가시키는 실험을 하였다. 직렬저항이 가장 낮았던 p ${\mu$}c$-Si:H/p a-SiC:H 로 p-layer 이중 증착에서 Voc는 0.95V F.F는 70% 이상이 나왔다. 이들 각 p층의 $E_a$(Activation Energy)를 구해본 결과, ${\mu$}c$-Si:H의 Ea 가 가장 낮은 것을 관찰 할 수 있었다.