• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.134-135
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• 2008

Ultra-thin $SiO_2/ZrO_2$ dielectrics were deposited by atomic layer chemical vapor deposition (ALCVD) method for non-volatile memory application. Metal-oxide-semiconductor (MOS) capacitors were fabricated by stacking ultra-thin $SiO_2$ and $ZrO_2$ dielectrics. It is found that the tunneling current through the stacked dielectric at the high voltage is lager than that through the conventional silicon oxide barrier. On the other hand, the tunneling leakage current at low voltages is suppressed. Therefore, the use of ultra-thin $SiO_2/ZrO_2$ dielectrics as a tunneling barrier is promising for the future high integrated non-volatile memory.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.255-255
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• 2010

Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.

• Korean Journal of Materials Research
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• v.5 no.2
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• pp.169-177
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• 1995

The diffusion barrier property of 100-nm-thick titanium nitride (TiN) film between Cu and Si was investigated using sheet resistance measurements, etch-pit observation, x-ray diffractometry, Auger electron spectroscopy, and transmission electron microscopy. The TiN barrier fails due to the formation of crystalline defects (dislocations) and precipitates (presumably Cu-silicides) in the Si substrate which result from the predominant in-diffusion of Cu through the TiN layer. In contrast with the case of Al, it is identified that the TiN barrier fails only the in-diffusion of Cu because there is no indication of Si pits in the Si substrate. In addition, it appears that the stuffing of TiN does not improve the diffusion barrier property in the Cu/TiN/Si structure. This indicates that in the case of Al, the chemical effect that impedes the diffusion of Al by the reaction of Al with $TiO_{2}$ which is present in the grain boundaries of TIN is very improtant. On the while, in the case of Cu, there is no chemical effect because Cu oxides, such as $Cu_{2}O$ or CuO, is thermodynamically unstable in comparison with $TiO_{2}$. For this reason, it is considered that the effect of stuffing of TiN on the diffusion barrier property is not significant in the Cu/ TiN/Si structure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.267-270
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• 2003

We have studied the interfacial diffusion phenomena and the role of ${\alpha}-Al_2O_3$ buffer layer as a diffusion barrier in the $Ba-ferrite/SiO_2$ magnetic thin films for high-density recording media. In the interface of amorphous Ba-ferrite ($1900-{\AA}-thick)/SiO_2$ thin film during annealing, the interfacial diffusion started to occur at ${\sim}700^{\circ}C$. As the annealing temperature increased up to $800^{\circ}C$, the interfacial diffusion abruptly proceeded resulting in the high interface roughness and the deterioration of the magnetic properties. In order to control the interfacial diffusion at the high temperature, we introduced ${\alpha}-Al_2O_3$ buffer layer ($110-{\AA}-thick$) in the interface of $Ba-ferrite/SiO_2$ thin film. During the annealing of $Ba-ferrite/{\alpha}-Al_2O_3/SiO_2$ thin film even at ${\sim}800^{\circ}C$, the interface was very smooth. The smooth interface of the film was also clearly shown by the cross-sectional FESEM. The magnetic properties, such as saturation magnetization 3nd intrinsic coercivity, were also enhanced, due to the inhibition of interfacial diffusion by the ${\alpha}-Al_2O_3$ buffer layer. Our study suggests that the ${\alpha}-Al_2O_3$ buffer layer act as a useful interfacial diffusion barrier in the $Ba-ferrite/SiO_2$ thin films.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.24-25
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• 2008

The effect of heat treatment in $HfO_2$ as charge trap with $SiO_2/Si_3N_4/SiO_2$ as tunnel oxide layer in capacitors has been investigated. Rapid thermal annealing (RTA) were carried out at the temperature range of 600 - $900^{\circ}C$. It is found that all devices carried out heat treatment have large threshold voltage shift Especially, device performed heat treatment at $900^{\circ}C$ has been confirmed the largest memory window. Also, Threshold voltage shift of device used conventional $SiO_2$ as tunnel oxide layer was smaller than that with $SiO_2/Si_3N_4/SiO_2$.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.229-229
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• 2010

With the scaling down of ultra large integrated circuits (ULSI) to the sub-50 nm technology node, the need for an ultra-thin, continuous and conformal diffusion barrier and Cu seed layer is increasing. However, diffusion barrier and Cu seed layer formation with a physical vapor deposition (PVD) method has become difficult as the technology node is reduced to 30 nm and beyond. Recent work on self-forming barrier processes using PVD Cu alloys have attracted great attention due to the capability of conformal ultra-thin barrier formation using a simple technique. However, as in the case of the conventional barrier and Cu seed layer, PVD of the Cu alloy seed layer will eventually encounter the difficulty in conformal deposition in narrow line trenches and via holes. Atomic layer deposition (ALD) has been known for its good step coverage and precise thickness control, and is a candidate technique for the formation of a thin conformal barrier layer and Cu seed layer. Conformal Cu-Mn seed layers were deposited by plasma enhanced atomic layer deposition (PEALD) at low temperature ($120^{\circ}C$), and the Mn content in the Cu-Mn alloys were controlled form 0 to approximately 10 atomic percent with various Mn precursor feeding times. Resistivity of the Cu-Mn alloy films decreased by annealing due to out-diffusion of Mn atoms. Out-diffused Mn atoms were segregated to the surface of the film and interface between a Cu-Mn alloy and $SiO_2$, resulting in self-formed $MnO_x$ and $MnSi_xO_y$, respectively. No inter-diffusion was observed between Cu and $SiO_2$ after annealing at $500^{\circ}C$ for 12 h, indicating an excellent diffusion barrier property of the $MnSi_xO_y$. The adhesion between Cu and $SiO_2$ was enhanced by the formation of $MnSi_xO_y$. Continuous and conductive Cu-Mn seed layers were deposited with PEALD into 32 nm $SiO_2$ trench, enabling a low temperature process, and the trench was perfectly filled using electrochemical plating (ECD) under conventional conditions. Thus, it is the resultant self-forming barrier process with PEALD Cu-Mn alloy film as a seed layer for plating Cu that has further potential to meet the requirement of the smaller than 30 nm node.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.11a
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• pp.186-186
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• 2012

최근 Flexible organic electronics 분야에 대한 관심과 더불어 소자의 산소 및 수분의 침투를 방지하기 위한 투습방지막 연구가 활발히 진행되고 있다. 이에 본 연구에서는 Closed Drift Linear Source(CDLPS) 플라즈마 공정을 이용하여 저온 고속의 $SiO_xC_yH_z$ barrier flims 형성 연구를 진행하였다. HMDSO(hexamethyldisiloxane), TMS(trimethylsilane)와 산소를 기반으로 HMDSO/HMDSO+산소의 비율에 따라 $Si(-O_x)$ 변화에 따른 특성 평가를 진행하였다. X-ray photoelectrom spectroscopy(XPS) 및 Ft-IR spectrometer 측정 시 3.7% 비율에서 실리콘 원소가 산소 라디칼과 효율적인 반응을 함으로써 단일한 $SiO_2$ 박막이 형성됨을 확인 하였다. 그와 반면에 비율의 증가로 인해 다량의 HMDSO 물질이 주입 되었을 시 산소 라디칼과 충분히 반응 되지 못하여 $SiO_2$에 비해 $Si(CH)_x$ 가 많이 함량 된 Polymer like한 $SiO_x$가 많이 형성되었다. 박막의 증착율의 경우에는 3.7%에서 18%로 증가함에 따라 35 nm/min에서 180 nm/min의 증착율을 가지는 것을 확인 하였다. 3.7% 비율의 단일 $SiO_2$ 공정 조건으로 유기태양전지에 형성 하였을 시 소자의 에너지 변환 효율(PCE)이 변화 없는 것을 확인하였다. 이는 기존 공정에 비해 CDLPS 플라즈마 공정의 경우 유기소자에 플라즈마로 인한 열에너지나 이온 충격 에너지로 인한 영향 없는 것을 확인 할 수 있다. 이런 장점을 통해 CDSPS를 이용한 공정 기술은 다양한 유기 소자의 barrier 형성 연구에 큰 도움이 될 것이다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.283-284
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• 2008

Electrical and optical characteristics of indium tin oxide (ITO) and indium zinc oxide (IZO) films without and with $(SiO_2)_3(ZnO)_7$ at.% (SZO) film deposited on poly(ethylene naphthalate) (PEN) and poly(ethylene terephthalate (PET) substrates as a gas barrier layer for flexible display were studied. The ITO and IZO films with SZO gas barrier layer showed the improved properties which were both the high transmittance of average 80% in the visible light range and the decreased sheet resistance as compared to those of ITO and IZO films without SZO layer. Particularly, the PEN substrate with only SZO gas barrier layer had a low water vapor transmission rate (WVTR) of $\sim10^{-3}g/m^2$/day. Thus, we suggest that the SZO film with protection ability against the water vapor permeation can be applied to gas barrier layer for flexible display.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.2 s.39
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• pp.15-19
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• 2006

The resistance switching characteristics of amorphous $SiO_2$ and poly-crystalline $TiO_2$ were investigated. Both films exhibit well defined switching characteristics with low and high resistance states. From I-V curve analyses, it was found that the low resistance states of both films obey an ohmic conduction mechanism and the high resistance states show generation of a Schottky potential barrier. Regarding the mechanism for resistance switching of the binary oxide, it is suggested that the generation and annihilation of potential barriers accounts for the changes to the high resistance state and low resistance state, respectively. The device operation characteristic parameters such as reset and set voltages of $TiO_2$ are distinctly smaller than those of $SiO_2$, indicating that the values are related to the dielectric constant.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.1
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• pp.81-87
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• 2010

In this paper, we have fabricated $SiO_2$ oxidation thin films by HDP-CVD(high density plasma-chemical vapor deposition) method for passivation layer or barrier layer of OLED(organic light emitting diode). We have control and estimate the deposition rate and relative index characteristics with process parameters and get optimized conditions. They are gas flow rate($SiH_4:O_2$=30:60[sccm]), 70 [mm] distance from source to substrate and no-bias. The WVTR(water vapor transmission rate) is 2.2 [$g/m^2$_day]. Therefore fabricated thin film can not be applied as passivation layer or barrier layer of OLED.