• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2002년도 춘계학술발표회 초록집
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• pp.49-49
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• 2002

독립된 티타늄(Ti)과 실리콘(Si) 타켓을 사용하여 DC reactive magnetron co-sputtering 공 정으로 Ti-Si-N 코탱막을 SKD 11 합금강위에 합성하였다. 고분해능 TEM 및 XPS 분석들로부터 Ti-Si-N 코탱막은 나노미터 크기의 TiN결정체들이 비정질 Si3N4 기지에 분산된 나노복합체의 마세구조를 냐타내었다. 코탱막의 경도는 11 at.%의 Si 함량에서 39 GPa의 최 고 경도값을 나타내었고 이 경우 미셰조직은 5nm 크기의 미세한 TiN 결정이 비정절상의 기지에 균일하게 분포된 특성을 보였다 .. Ti-Si-N 박막내에 Si 함량이 증가할수록 TiN 결정 상들은 다배향성을 나타내었고 크기가 감소하였으며 비정질상에 의해 완전히 둘려싸언 형상 으로 변화하였다. 높은 Si 함량에서는 질소 소스의 부족현상에 의하여 코팅막내에서 free Si 가 나타났다. 상대습도가 증가함에 따라 Ti-Si-N 코탱막의 마찰계수와 마모량이 현저하게 감소하였다. 강재에 대한 Ti-Si-N 코팅막의 마모거동에 있어서 Si02 냐 Si(OH)2 같은 얇은 윤활막의 형성이 중요한 역할을 하는 것으로 판단되어졌다.

• 한국세라믹학회:학술대회논문집
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• 한국세라믹학회 2002년도 추계총회 및 연구발표회 초록집
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• pp.114.2-114
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• 2002

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.221-221
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• 2013

Striving to replace the well known silicon nanocrystals embedded in oxides with solution-processable charge-trapping materials has been debated because of large scale and cost effective demands. Herein, a silicon quantum dot-polystyrene nanocomposite (SiQD-PS NC) was synthesized by postfunctionalization of hydrogen-terminated silicon quantum dots (H-SiQDs) with styrene using a thermally induced surface-initiated polymerization approach. The NC contains two miscible components: PS and SiQD@PS, which respectively are polystyrene and polystyrene chains-capped SiQDs. Spin-coated films of the nanocomposite on various substrate were thermally annealed at different temperatures and subsequently used to construct metal-insulator-semiconductor (MIS) devices and thin film field effect transistors (TFTs) having a structure p-$S^{++}$/$SiO_2$/NC/pentacene/Au source-drain. C-V curves obtained from the MIS devices exhibit a well-defined counterclockwise hysteresis with negative fat band shifts, which was stable over a wide range of curing temperature ($50{\sim}250^{\circ}C$. The positive charge trapping capability of the NC originates from the spherical potential well structure of the SiQD@PS component while the strong chemical bonding between SiQDs and polystyrene chains accounts for the thermal stability of the charge trapping property. The transfer curve of the transistor was controllably shifted to the negative direction by chaining applied gate voltage. Thereby, this newly synthesized and solution processable SiQD-PS nanocomposite is applicable as charge trapping materials for TFT based memory devices.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.37-37
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• 2008

Hydrogenated nanocrystalline Si (nc-Si:H) thin films were prepared by plasma enhanced chemical vapor deposition (PECVD). The films were deposited with a radio frequency power of 100 W, while substrates were exposed to direct current (DC) biases in the range from 0 to -400 V. The effects of the DC bias on the formation of nanoscale Si crystallites in the films and on their optical characteristics were investigated. The size of the Si crystallites in the films ranges from ~ 1.9 to ~ 4.1 nm. The relative fraction of the crystallites in the films reached up ~ 56.5 % when the DC bias of -400 V was applied. Based on the variation in the structural, chemical, and optical features of the films with DC bias voltages, a model for the formation of nanostructures of the nc-Si:H films prepared by PECVD was suggested. This model can be utilized to understand the evolution in the size and relative fraction of the nanocrystallites as well as the amorphous matrix in the nc-Si:H films.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1281_1282
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• 2009

ICP-CVD를 이용하여 inverted staggered 구조를 갖는 미세결정 실리콘 (Nanocrystalline Silicon, nc-Si) 박막 트랜지스터(Thin Film Transistor, TFT)를 제작하였다. 또한, 소자의 특성과 전기적 안정성을 평가하였다. 실험 결과는 짧은 채널 길이를 갖는 nc-Si TFT가 긴 채널 길이의 소자보다 같은 드레인 전압 바이어스 하에서 덜 열화 됨을 알 수 있었다. 이는 드레인 전압 바이어스 하에서의 낮은 채널 캐리어 농도는 적은 defect state를 만들기 때문으로 짧은 채널 길이의 TFT가 긴 채널 길이의 TFT보다 $V_{TH}$ 열화가 적었다. 이러한 결과는 짧은 채널 길이의 nc-Si TFT가 디스플레이 분야에 있어 다양하게 응용될 것으로 기대된다.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2012년도 추계총회 및 학술대회 논문집
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• pp.111-111
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• 2012

• 한국재료학회지
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• 제29권5호
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• pp.317-321
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• 2019

We investigated the characteristics of nano crystalline silicon(nc-Si) thin-film solar cells on graphite substrates. Amorphous silicon(a-Si) thin-film solar cells on graphite plates show low conversion efficiency due to high surface roughness, and many recombination by dangling bonds. In previous studies, we deposited barrier films by plasma enhanced chemical vapor deposition(PECVD) on graphite plate to reduce surface roughness and achieved ~7.8 % cell efficiency. In this study, we fabricated nc-Si thin film solar cell on graphite in order to increase the efficiency of solar cells. We achieved 8.45 % efficiency on graphite plate and applied this to nc-Si on graphite sheet for flexible solar cell applications. The characterization of the cell is performed with external quantum efficiency(EQE) and current density-voltage measurements(J-V). As a result, we obtain ~8.42 % cell efficiency in a flexible solar cell fabricated on a graphite sheet, which performance is similar to that of cells fabricated on graphite plates.

• 한국표면공학회지
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• 제35권3호
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• pp.133-140
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• 2002

The Ti-Si-N coating layers were synthesized on SKD 11 steel substrate by a DC reactive magnetron co-sputtering technique with separate Ti and Si targets. The high resolution transmission electron microscopy (HRTEM) and X-ray photoelectron spectroscopy (XPS) analyses for the coating layers revealed that microstructure of Ti-Si-N layer was nanocomposite, consisting of nano-sized TiN crystallites surrounded by amorphous $Si_3$$N_4$ phase. The highest hardness value of about 39 GPa was obtained at the Si content of ~11at.%, where the microstructure had fine TiN crystallites (about 5nm in size) dispersed uniformly in amorphous matrix. As the Si content in Ti-Si-N films increased, the TiN crystallites became from aligned to randomly oriented microstructure, finer, and fully penetrated by amorphous phase. Free Si appeared in the layers due to the deficit of nitrogen source at higher Si content. Friction coefficient and wear rate of the Ti-Si-N coating layer significantly decreased with increase of relative humidity. The self-lubricating tribe-layers such as $SiO_2$ or (OH)$Si_2$ seemed to play an important role in the wear behavior of Ti-Si-N film against steel.

• Transactions on Electrical and Electronic Materials
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• 제2권2호
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• pp.16-20
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• 2001

Optoelectronic characteristics of the superlattice diode as a function of deposition temperature and annealing conditions have been studied. The multilayer nanocrystalline silicon/adsorbed oxygen (nc/Si/O) superlattice formed by molecular beam epitaxy (MBE) system. Experimental results showed that deposition temperature of 550$^{\circ}C$, followed by hydrogen annealing leads to best results, in terms of optical photoluminescence (PL) and electrical current-voltage (I-V) characteristics. Consequently, the experimental results of multilayer Si/O superlattic device showed the stable photoluminescence and good insulating behavior with high breakdown voltage. This is very useful promise for Si-based optoelectronic devices, and can be readily integrated with conventional silicon ULSI processing.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1025-1027
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• 2009

Novel low temperature deposition process for nano-crystalline Si thin film is developed with the hyper-thermal neutral beam (HNB) technology. By our HNB assisted CVD system, the reactive particles can induce crystalline phase in Si thin films and effectively combine with heating effect on substrate. At low deposition temperature under $80^{\circ}C$, the HNB with proper incident energy controlled by the reflector bias can effectively enhance the nano-crystalline formation in Si thin film without any additional process. The electrical properties of Si thin films can be varied from a-Si to nc-Si according to change of HNB energy and substrate temperature. Characterization of these thin films with conductivity reveal that crystalline of Si thin film can increase by assist of HNB with appropriate energy during low temperature deposition. And low temperature prcoessed nc-Si TFT performance has on-off ratio as order 5.