• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.41.2-41.2
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Metal Oxide Semiconductor) based electronic devices become much faster speed and smaller size than ever before. However, very narrow interconnect line width causes some drawbacks. For example, deposition of conformal and thin barrier is not easy moreover metallization process needs deposition of diffusion barrier and glue layer. Therefore, there is not enough space for copper filling process. In order to overcome these negative effects, simple process of copper metallization is required. In this research, Cu-V thin alloy film was formed by using RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane $SiO_2$/Si bi-layer substrate with smooth and uniform surface. Cu-V film thickness was about 50 nm. Cu-V layer was deposited at RT, 100, 150, 200, and $250^{\circ}C$. XRD, AFM, Hall measurement system, and XPS were used to analyze Cu-V thin film. For the barrier formation, Cu-V film was annealed at 200, 300, 400, 500, and $600^{\circ}C$ (1 hour). As a result, V-based thin interlayer between Cu-V film and $SiO_2$ dielectric layer was formed by itself with annealing. Thin interlayer was confirmed by TEM (Transmission Electron Microscope) analysis. Barrier thermal stability was tested with I-V (for measuring leakage current) and XRD analysis after 300, 400, 500, 600, and $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However V-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Thus, thermal stability of vanadium-based thin interlayer as diffusion barrier is good for copper interconnection.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.234-235
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• 2008

The surface flatness of heteroepitaxially grown 3C-SiC thin films is a key factor affecting electronic and mechanical device applications. This paper describes the surface flatness of poly(polycrystalline) 3C-SiC thin films according to Ar flow rates and the geometric structures of reaction tube, respectively. The poly 3C-SiC thin film was deposited by APCVD (Atmospheric pressure chemical vapor deposition) at $1200^{\circ}C$ using HMDS (Hexamethyildisilane : $Si_2(CH_3)_6)$ as single precursor, and 1~10 slm Ar as the main flow gas. According to the increase of main carrier gas, surface fringes and flatness are improved. It shows the distribution of thickness is formed uniformly.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.194-194
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• 2009

3C-SiC thin films are widely used in extreme environments, radio frequency (RF) environments, and bio-materials for micro/nano electronic mechanical systems (M/NEMS). The mechanical properties of 3C-SiC thin films need to be considered when designing M/NEMS, so Young's Modulus and the hardness need to be accurately measured. Young's Modulus and the hardness are influenced by N-doping. In this paper, we show that the mechanical properties of poly (polycrystalline) 3C-SiC thin films are influenced by the N-doping concentration. Furthermore, we measure the mechanical properties of 3C-SiC thin films for N-doping concentrations of 1%, 3%, and 5%, by using nanoindentation. For films deposited using a 1% N-doping concentration, Young's Modulus and the hardness were measured as 270 GPa and 30 GPa, respectively. When the surface roughness of the thin films was investigated by using atomic force microscopy (AFM), the roughness of the 5% N-doped 3C-SiC thin film was the lowest of all the films, at 15 nm.

• Solar Energy
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• v.11 no.3
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• pp.74-83
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• 1991

In this study, the (p)ZnTe/(n)Si solar cell and (n)CdS-(p)ZnTe/(n)Si poly-junction thin film are fabricated by vaccum deposition method at the substrate temperature of $200{\pm}1^{\circ}C$ and then their electrical properties are investigated and compared each other. The test results from the (p)ZnTe/(n)Si solar cell the (n)CdS-(p)ZnTe/(n)Si poly-junction thin fiim under the irradiation of solar energy $100[mW/cm^2]$ are as follows; Short circuit current$[mA/cm^2]$ (p)ZnTe/(n)Si:28 (n)CdS-(p)ZnTe/(n)Si:6.5 Open circuit voltage[mV] (p)ZnTe/(n)Si:450 (n)CdS-(p)ZnTe/(n)Si:250 Fill factor (p)ZnTe/(n)Si:0.65 (n)CdS-(p)ZnTe/(n)Si:0.27 Efficiency[%] (p)ZnTe/(n)Si:8.19 (n)CdS-(p)ZnTe/(n)Si:2.3 The thin film characteristics can be improved by annealing. But the (p)ZnTe/(n)Si solar cell are deteriorated at temperatures above $470^{\circ}C$ for annealing time longer than 15[min] and the (n)CdS-(p)ZnTe/(n)Si thin film are deteriorated at temperature about $580^{\circ}C$ for longer than 15[min]. It is found that the sheet resistance decreases with the increase of annealing temperature.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.1
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• pp.65-69
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• 2003

ZnO-Si-ZnO multi-layer thin films have been deposited by pulsed laser deposition (PLD). And then, the films have been annealed at 300$^{\circ}C$ in oxygen ambient pressure. Peak positions of ultraviolet (UV) and visible region were changed by addition of Si layer. Mobility of the films was improved slightly than ZnO thin film without Si layer. The structural property changed by inserting intermediate Si layer in ZnO thin film. The optical properties and structural properties of ZnO-Si-ZnO multi-layer thin films were characterized by PL(Photoluminescence) and XRB(X-ray diffraction) method, respectively. Electrical properties were measured by van der Pauw Hall measurements

• Journal of Electrical Engineering and Technology
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• v.2 no.4
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• pp.525-531
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• 2007

Ni(75 wt.%)-Cr(20 wt.%)-Al(3 wt.%)-Mn(4 wt.%)-Si(1 wt.%) alloy thin films were prepared using the DC magnetron sputtering process by varying the sputtering conditions such as power, pressure, substrate temperature, and post-deposition annealing temperature in order to fabricate a precision thin film resistor. For all the thin film resistors, sheet resistance, temperature coefficient of resistance (TCR), and crystallinity were analyzed and the effects of sputtering conditions on their properties were also investigated. The oxygen content and TCR of Ni-Cr-Al-Mn-Si resistors were decreased by increasing the sputtering pressure. Their sheet resistance, TCR, and crystallinity were enhanced by elevating the substrate temperature. In addition, the annealing of the resistor thin films in air at a temperature higher than $300^{\circ}C$ lead to a remarkable rise in their sheet resistance and TCR. This may be attributed to the improved formation of NiO layer on the surface of the resistor thin film at an elevated temperature.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.67-68
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• 2000

Polycrystalline silicon (poly-Si) thin film transistors (TFT's) employing vertical amorphous silicon (a-Si) offsets have been fabricated without additional photolithography processes. The a-Si offset has been formed utilizing the poly-Si grain growth blocking effect by thin native oxide film during the excimer laser recrystallization of a-Si. The ON current degradation of the new device after 4 hour's electrical stress was reduced by 5 times compared with conventional poly-Si TFT's.

• Journal of the Korean Ceramic Society
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• v.35 no.5
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• pp.486-492
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• 1998

Silicon carbide (SiC) thin films were deposited on the porous silicon substrates by chemical vapour de-position(CVD) using MTS as a source material. The deposited films were ${\beta}$-SiC with poor crystallity con-firmed by XRD measurement. It was considered that the films showed the mixed characteistics of cry-stalline and amorphous SiC where amorphous SiC where amorphous SiC played a role of buffer layer in interface between as-dep films and Si substrate. The buffer layer reduced lattice mismatch to some extent the generally occurs when SiC films are deposited on Si. The low temperature (10K) PL (phtoluminescence) studies showed two broad bands with peaks at 600 and 720 for the films deposited at 1100$^{\circ}C$ The maximum PL peak of the crystalline SiC was observed at 600 nm and the amrophous SiC of 720 nm was also confirmed. PL peak due the amorphous SiC was smaller than that of the crystalline SiC, PL of porous Si might be disapperared due to densification during heat treatment.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.6
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• pp.439-444
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• 2012

For the application of photo-detector as active layer, we have studied how to deposit SiGe thin film using an independent Si target and Ge target, respectively. Both targets were synthesized by purity of 99.999%. Plasma generators were generated by radio frequency (rf, 13.56 MHz) and direct current (dc) power. When Ge and Si targets were sputtered by dc and rf power, respectively, we could observe the growth of highly crystalline Ge thin film at the temperature of $400^{\circ}C$ from the result of raman spectroscopy and X-ray diffraction method. However, SiGe thin film did not deposit above method. Inversely, we changed target position like that Ge and Si targets were sputtered by rf and dc power, respectively. Although Ge crystalline growth without Si target sputtering deteriorated considerably, the growth of SiGe thin film was observed with increase of Si dc power. SiGe thin film was evaluated as microcrystalline phase which included (111) and (220) plane by X-ray diffraction method.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.4
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• pp.33-39
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• 1997

The crystallization temperature of an amorphous silicon (a-Si) can be lowered down to 400.deg. C by a new method : Double-metal induced lateral crystallization (DMILC). The a-Si film was laterally crystallized from Ni and Pd deposited area, and its lateral crystallization rate reaches up to 0.2.mu.m/hour at that temperature and depends on the overlap length of Ni and Pd films; the shorter the overlap length, the faster the rate. Poly-Silicon thin film transistors (poly-Si TFT's) fabricated by DMILC at 400.deg. C show a field effect mobility of 38.5cm$^{3}$/Vs, a minimum leakage current of 1pA/.mu.m, and a slope of 1.4V/dec. The overlap length does not affect the characteristics of the poly-Si TFT's, but determines the lateral crystallization rate.