• 한국재료학회지
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• 제19권9호
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• pp.462-467
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• 2009

The Charge Trap Flash (CTF) memory device is a replacement candidate for the NAND Flash device. In this study, Pt/$Al_2O_3/La_2O_3/SiO_2$/Si multilayer structures with lanthanum oxide charge trap layers were fabricated for nonvolatile memory device applications. Aluminum oxide films were used as blocking oxides for low power consumption in program/erase operations and reduced charge transports through blocking oxide layers. The thicknesses of $SiO_2$ were from 30 $\AA$ to 50 $\AA$. From the C-V measurement, the largest memory window of 1.3V was obtained in the 40 $\AA$ tunnel oxide specimen, and the 50 $\AA$ tunnel oxide specimen showed the smallest memory window. In the cycling test for reliability, the 30 $\AA$ tunnel oxide sample showed an abrupt memory window reduction due to a high electric field of 9$\sim$10MV/cm through the tunnel oxide while the other samples showed less than a 10% loss of memory window for $10^4$ cycles of program/erase operation. The I-V measurement data of the capacitor structures indicated leakage current values in the order of $10^{-4}A/cm^2$ at 1V. These values are small enough to be used in nonvolatile memory devices, and the sample with tunnel oxide formed at $850^{\circ}C$ showed superior memory characteristics compared to the sample with $750^{\circ}C$ tunnel oxide due to higher concentration of trap sites at the interface region originating from the rough interface.

• 한국전기전자재료학회논문지
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• 제26권4호
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• pp.271-274
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• 2013

Power Metal Oxide Semiconductor Field Effect Transistor's (MOSFETs) are well known for superior switching speed, and they require very little gate drive power because of the insulated gate. In these respects, power MOSFETs approach the characteristics of an "ideal switch". The main drawback is on-resistance RDS(on) and its strong positive temperature coefficient. While this process has been driven by market place competition with operating parameters determined by products, manufacturing technology innovations that have not necessarily followed such a consistent path have enabled it. This treatise briefly examines metal oxide semiconductor (MOS) device characteristics and elucidates important future issues which semiconductor technologists face as they attempt to continue the rate of progress to the identified terminus of the technology shrink path in about 2020. We could find at the electrical property as variation p base dose. Ultimately, its ON state voltage drop was enhanced also shrink chip size. To obtain an optimized parameter and design, we have simulated over 500 V Field ring using 8 Field rings. Field ring width was $3{\mu}m$ and P base dose was $1e15cm^2$. Also the numerical multiple $2.52cm^2$ was obtained which indicates the doping limit of the original device. We have simulated diffusion condition was split from $1,150^{\circ}C$ to $1,200^{\circ}C$. And then $1,150^{\circ}C$ diffusion time was best condition for break down voltage.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.64-64
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• 2009

Atomic force microscopy (AFM) fabrication of oxide patterns is an attractive technique for nanoscale patterns and related device structures, SiC exhibits good performance in high-power, high-frequency, and high-temperature conditions that is comparable to the performance of Si. The AFM fabrication of oxide patterns on SiC is important for electronic applications. However, there has not been much reported investigations on oxidation of SiC using AFM. We achieved the local oxidation of 4H-SiC using the high loading force of ~100 nN, although the oxidation of SiC is generally difficult mainly due to the physical hardness and chemical inactivity. All the experiments were performed using atomic force microscopy (S.I.S. GmbH, Germany) with a Pt/Ir-coated Si tip at ~40% humidity and room temperature. The spring constant and resonance frequency of the tip were around ~3 N/m and ~70 kHz. We fabricated oxide patterns on n-type 4H-SiC ($\sim10^{19}/cm^3$) and n-type Si ($\sim1.9\times10^{16}/cm^3$). In summary, we demonstrated that the oxide patterns can be obtained over the electric field of ${\sim}\times10^7 V/cm$ and the high loading force using the tip as a cathode. The electric field transports the oxyanions (OH-) to the positively biased surface.

• 진공이야기
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• 제3권3호
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• pp.15-18
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• 2016

In future wearable electronic systems, 3-dimensional (3D) devices have attracted much attention due to their high density integration and low-power functionality. Among 3D devices, gate-all-around (GAA) nanowire transistor provides superior gate controllability, resulting in suppressing short channel effect and other drawbacks in 2D metal-oxide-semiconductor field-effect transistor (MOSFET). Silicon nanowires (SiNWs) are the most promising building block for GAA structure device due to their compatibility with the current Si-based ultra large scale integration (ULSI) technology. Moreover, the theoretical limit for subthreshold swing (SS) of MOSFET is 60 mV/dec at room temperature, which causes the increase in Ioff current. To overcome theoretical limit for the SS, it is crucial that research into new types of device concepts should be performed. In our present studies, we have experimentally demonstrated feedback FET (FBFET) and tunnel FET (TFET) with sub-60 mV/dec based on SiNWs. Also, we fabricated SiNW based complementary TFET (c-TFET) and SiNW complementary metal-oxide-semiconductor (CMOS) inverter. Our research demonstrates the promising potential of SiNW electronic devices for future wearable electronic systems.

• 한국결정성장학회지
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• 제8권4호
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• pp.640-644
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• 1998

Sb/SiC(4H) 및 Ti/SiC(4H) 쇼트키 다이오드(SBD)를 제작하여 그 특성을 조사하였다. 용량-전압(C-V) 측정으로부터 얻은 n-형 SiC(4H)의 주개(donor) 농도는 약 $2.5{\times}10 ^{17}{\textrm}cm^{-3}$이었다. 순방향 전류-전압(I-V) 특성의 기울기로부터 얻은 Sb/SiC(4H) 쇼트키 다이오드의 이상계수는 1.31이었고, 역방향 항복전장(breakdown field)은 약 4.4$\times$102V/cm 이었다. 용량-전압(C-V) 측정으로부터 얻은 Sb/SiC(4H) SBD의 내부전위(built-in potential) 및 쇼트키 장벽 높이는 각각 1.70V 및 1.82V이었다. Sb/SiC(4H)의 장벽높이 1.82V는 Ti/SiC(4H)의 0.91V보다 높았다. 그러나 Sb/SiC(4H)의 전류밀도와 역방향 항복전장은 Ti/SiC(4H)의 것보다 낮았다. Ti/SiC(4H)는 물론 Sb/SiC(4H) 쇼트키 다이오드는 고전력 전자소자로서 유용하다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.535-536
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• 2005

Organic photovoltaic effects were studied in a device structure of ITO/CuPc/Al and ITO/CuPc/$C_{60}$/BCP/Al. A thickness of CuPc layer was varied from 10 nm to 50 nm, we have obtained that the optimum CuPc layer thickness is around 40 nm from the analysis of the current density-voltage characteristics in CuPc single layer photovoltaic cell. From the thickness-dependent photovoltaic effects in CuPc/$C_{60}$ heterojunction devices, higher power conversion efficiency was obtained in ITO/20nm CuPc/40nm $C_{60}$/Al, which has a thickness ratio (CuPc:$C_{60}$) of 1:2 rather than 1:1 or 1:3. Light intensity on the device was measured by calibrated Si-photodiode and radiometer/photometer of International Light Inc(IL14004).

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권8호
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• pp.319-324
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• 2003

AIN thin films are deposited on Si (100) and $SiO_2$/Si substrates by using an RF magnetron sputtering method and by changing the conditions of deposition variables, such as RF power, $N_2$/Ar flow ratio, and substrate temperature ($T_sub$). For all the deposited AIN films, XRD Peak patterns are monitored to examine the effect of deposition condition on the crystal orientation. Highly (002)-oriented AIN films are obtained at following nominal deposition conditions; RF Power : 350W, $N_2$/Ar ratio = 10/20, T$_{sub}$ : $250^{\circ}C$, and working pressure = 5mTorr, respectively. AIN-based SAW devices are fabricated using a lift-off method by varying the thickness of AIN layer. Insertion losses and side-lobe rejection levels of fabricated SAW devices are extracted from their frequency response characteristics, which are also compared in terms of AIN thickness and substrate. Relationships between the film properties of AIN films and the frequency responses of SAW devices are discussed. It is concluded from the experimental results that the (002)-preferred orientation as well as the surface roughness of AIN film may play a crucial role of determining the device performances of AIN-SAW devices.s.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.322-322
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• 2010

For boron doping on n-type silicon wafer, around $1,000^{\circ}C$ doping temperature is required, because of the relatively low solubility of boron in a crystalline silicon comparing to the phosphorus case. Boron doping by fiber laser annealing and lamp furnace heat treatment were carried out for the uniformly deposited p-a-Si:H layer. Since the uniformly deposited p-a-Si:H layer by cluster is highly needed to be doped with high temperature heat treatment. Amorphous silicon layer absorption range for fiber laser did not match well to be directly annealed. To improve the annealing effect, we introduce additional lamp furnace heat treatment. For p-a-Si:H layer with the ratio of $SiH_4:B_2H_6:H_2$=30:30:120, at $200^{\circ}C$, 50 W power, 0.2 Torr for 30 min. $20\;mm\;{\times}\;20\;mm$ size fiber laser cut wafers were activated by Q-switched fiber laser (1,064 nm) with different sets of power levels and periods, and for the lamp furnace annealing, $980^{\circ}C$ for 30 min heat treatment were implemented. To make the sheet resistance expectable and uniform as important processes for the $p^+$ layer on a polished n-type silicon wafer of (100) plane, the Q-switched fiber laser used. In consequence of comparing the results of lifetime measurement and sheet resistance relation, the fiber laser treatment showed the trade-offs between the lifetime and the sheet resistance as $100\;{\omega}/sq.$ and $11.8\;{\mu}s$ vs. $17\;{\omega}/sq.$ and $8.2\;{\mu}s$. Diode level device was made to confirm the electrical properties of these experimental results by measuring C-V(-F), I-V(-T) characteristics. Uniform and expectable boron heavy doped layers by fiber laser and lamp furnace are not only basic and essential conditions for the n-type crystalline silicon solar cell fabrication processes, but also the controllable doping concentration and depth can be established according to the deposition conditions of layers.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 춘계종합학술대회 A
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• pp.744-746
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• 2008

Organic photovoltaic effects were studied in a device structure of ITO/CuPc/Al and ITO/CuPc/$C_{60}$/BCP/Al. A thickness of CuPc layer was varied from 10 nm to 50 nm, we have obtained that the optimum CuPc layer thickness is around 40 nm from the analysis of the current density-voltage characteristics in CuPc single layer photovoltaic cell. From the thickness-dependent photovoltaic effects in CuPc/$Cu_{60}$ heterojunction devices, higher power conversion efficiency was obtained in ITO/20nm CuPc/40nm $C_{60}$/Al, which has a thickness ratio (CuPc:$C_{60}$) of 1:2 rather than 1:1 or 1:3. Light intensity on the device was measured by calibrated Si-photodiode and radiometer/photometer of International Light Inc(IL14004).

• 전기전자학회논문지
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• 제17권4호
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• pp.428-433
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• 2013

본 논문에서는 전력반도체 소자의 재료로써 주목받고 있는 탄화규소 기반의 Trench MOS Barrier Schottky(TMBS)의 순방향 및 역방향 특성을 개선시키기 위한 구조를 제안한다. 순방향 전압강하와 역방향 항복전압을 개선시키기 위하여 사다리꼴 mesa 구조와 trench sidewall의 길이를 조절하는 기법을 사용하는 4H-SiC TMBS 정류기를 제안하고 있다. 제안된 구조는 사다리꼴 mesa 구조를 적용하여 trench sidewall에 경사를 줌으로써 1508V의 역방향 항복전압을 얻었다. 이것은 기존의 4H-SiC TMBS 정류기에 비하여 역방향 항복전압을 11% 개선시켰음을 나타낸다. 또한 trench sidewall 상단의 길이를 조절하여 순방향 전류 $200A/cm^2$에 대하여 12% 감소된 1.6V의 순방향 전압강하를 얻었다. 제안된 소자는 Silvaco사의 T-CAD를 사용하여 전기적 특성을 분석하였다.