• KIEE International Transactions on Electrophysics and Applications
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• v.3C no.2
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• pp.66-69
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• 2003

Various semiconductor nanowires such as GaN, GaP, InP, Si$_3$N$_4$, SiO$_2$/Si, and SiC were coated conformally with aluminum oxide (Al$_2$O$_3$) layers by atomic layer deposition (ALD) using trimethylaluminum (TMA) and distilled water ($H_2O$) at a temperature of 20$0^{\circ}C$. Transmission electron microscopy (TEM) revealed that A1203 cylindrical shells conformally coat the semiconductor nanowires. This study suggests that the ALD of $Al_2$O$_3$ on nanowires is a promising method for preparing cylindrical dielectric shells for coaxially gated nanowire field-effect transistors.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04b
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• pp.95-95
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• 2009

Single-crystalline Bi nanowires have motivated many researchers to investigate novel quasi-one-dimensional phenomena such as the wire-boundary scattering effect and quantum confinement effects due to their electron effective mass (~0.001 me). Single crystalline Bi nanowires were found to grow on as-sputtered films after thermal annealing at $270^{\circ}C$. This was facilitated by relaxation of stress between the film and the thermally oxidized Si substrate that originated from a mismatch of the thermal expansion. However, the method is known to produce relatively lower density of nanowires than that of other nanowire growth methods for device applications. In order to increase density of nanowire, we propose a method for enhancing compressive stress which is a driving force for nanowire growth. In this work, we report that the compressive stress can be controlled by modifying a substrate structure. A combination of photolithography and a reactive ion etching technique was used to fabricate patterns on a Si substrate. It was found that the nanowire density of a Bi film grown on $100{\mu}m{\times}100{\mu}m$ pattern Si substrate increased over seven times higher than that of a Bi sample grown on a normal substrate. Our results show that density of nanowire can be enhanced by sidewall effect in optimized proper pattern sizes for the Bi nanowire growth.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.215-216
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• 2013

The silicide is a compound of Si with an electropositive component. Silicides are commonly used in silicon-based microelectronics to reduce resistivity of gate and local interconnect metallization. The popular silicide candidates, CoSi2 and TiSi2, have some limitations. TiSi2 showed line width dependent sheet resistance and has difficulty in transformation of the C49 phase to the low resistive C54. CoSi2 consumes more Si than TiSi2. Nickel silicide is a promising material to substitute for those silicide materials providing several advantages; low resistivity, lower Si consumption and lower formation temperature. Nickel silicide (NiSi) nanowire (NW) has features of a geometrically tiny size in terms of diameter and significantly long directional length, with an excellent electrical conductivity. According to these advantages, NiSi NWs have been applied to various nanoscale applications, such as interconnects [1,2], field emitters [3], and functional microscopy tips [4]. Beside its tiny geometric feature, NW can provide a large surface area at a fixed volume. This makes the material viable for photovoltaic architecture, allowing it to be used to enhance the light-active region [5]. Additionally, a recent report has suggested that an effective antireflection coating-layer can be made with by NiSi NW arrays [6]. A unique growth mechanism of nickel silicide (NiSi) nanowires (NWs) was thermodynamically investigated. The reaction between Ni and Si primarily determines NiSi phases according to the deposition condition. Optimum growth conditions were found at $375^{\circ}C$ leading long and high-density NiSi NWs. The ignition of NiSi NWs is determined by the grain size due to the nucleation limited silicide reaction. A successive Ni diffusion through a silicide layer was traced from a NW grown sample. Otherwise Ni-rich or Si-rich phase induces a film type growth. This work demonstrates specific existence of NiSi NW growth [7].

• Journal of the Korean Vacuum Society
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• v.19 no.4
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• pp.307-313
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• 2010

One-dimensional cubic phase silicon carbide nanowires (${\beta}$-SiC NWs) were efficiently synthesized by thermal chemical vapor deposition (TCVD) with mixtures containing Si powders and nickel chloride hexahydrate $(NiCl_2{\cdot}6H_2O)$ in an alumina boat with a carbon source of methane $(CH_4)$ gas. SEM images are shown that the growth temperature (T) of $1,300^{\circ}C$ is not enough to synthesize the SiC NWs owing to insufficient thermal energy for melting down a Si powder and decomposing the methane gas. However, the SiC NWs could be synthesized at T>$1,300^{\circ}C$ and the most efficient temperature for growth of SiC NWs is T=$1,400^{\circ}C$. The synthesized SiC NWs have the diameter with an average range between 50~150 nm. Raman spectra clearly revealed that the synthesized SiC NWs are forming of a cubic phase (${\beta}$-SiC). Two distinct peaks at 795 and $970 cm^{-1}$ in Raman spectra of the synthesized SiC NWs at T=$1,400^{\circ}C$ represent the TO and LO mode of the bulk ${\beta}$-SiC, respectively. XRD spectra are also supported to the Raman spectra resulting in the strongest (111) peaks at $2{\Theta}=35.7^{\circ}$, which is the (111) plane peak position of 3C-SiC. Moreover, the gas flow rate of 300 sccm for methane is the optimal condition for synthesis of a large amount of ${\beta}$-SiC NW without producing the amorphous carbon structure shown at a high methane flow rate of 800 sccm. TEM images are shown two kinds of the synthesized ${\beta}$-SiC NWs structures. One is shown the defect-free ${\beta}$-SiC NWs with a (111) interplane distance of 0.25 nm, and the other is the stacking-faulted ${\beta}$-SiC NWs. Also, TEM images exhibited that two distinct SiC NWs are uniformly covered with $SiO_2$ layer with a thickness of less 2 nm.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.77.2-77.2
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• 2015

Recently, metamaterials attracted much attention because of the potential applications for superlens, cloaking and high precision sensors. We developed several dielectric metamaterials for enhancing antireflection or light trapping capability in solar energy harvesting devices. Colloidal lithography and electrochemical anodization process were employed to fabricate self-assembed nano- and microscale dielectric metamaterials in a simple and cost-effective manner. We improved broadband light absorption in c-Si, a-Si, and organic semiconductor layer by employing polystyrene (PS) islands integrated Si conical-frustum arrays, resonant PS nanosphere arrays, and diffusive alumina nanowire arrays, respectively. We also demonstrated thin metal coated alumina nanowire array which is utilized as an efficient light-to-heat conversion layer of solar steam generating devices. The scalable design and adaptable fabrication route to our light management nanostructures will be promising in applications of solar energy harvesting system. On the other hands, broadband invisible cloaks, which continuously work while elastically deforming, are developed using smart metamaterials made of photonic and elastic crystals. A self-adjustable, nearly lossless, and broadband (10-12GHz) smart meatamaterials have great potentials for applications in antenna system and military stealth technology.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.08a
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• pp.120-120
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• 2009

• Journal of Korean Vacuum Science & Technology
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• v.6 no.2
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• pp.79-83
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• 2002

As Ag does not form my silicide on Si surfaces, Ag wire is a candidate for self-assembled nanowire on the reconstructed and single-domain Si(5 5 12)-2 $\times$ 1. In the present study, various Ag coverages and post-annealing temperatures had been tested to fabricate a Ag nanowire with high aspect ratio. When Ag coverage was less than 0.03 ML and the post-annealing temperature was 500(C, Ag atoms preferentially adsorbed on the tetramer sites resulting in Ag wires with an inter-row spacing of ~5 nm. However, its aspect ratio is relatively small and its height is also not even. On the other hand, the Ag-posited surface completely loses its reconstruction even with the same annealing at 500 $\^{C}$ if the initial coverage exceeds 0.05 ML. But the additional subsequent annealing at 700$\^{C}$ and slow-cooling process recovers the well-ordered Ag chain with relatively high aspect ratio on the same tetramer sites. It can be understood that, in the double step annealing process, the lower temperature annealing is required for cohesion of adsorbed Ag atoms and the higher temperature annealing is for providing Ag atoms to the tetramer sites.

• Journal of the Korean Ceramic Society
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• v.55 no.3
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• pp.285-289
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• 2018

We synthesized silicon carbide (${\beta}-SiC$) nanowires with nano-scale diameter (30 - 400 nm) and micro-scale length ($50-200{\mu}m$) on a porous body using low-grade silica and carbon black powder by carbothermal reduction at $1300-1600^{\circ}C$. The SiC nanowires were formed by vapor-liquid-solid deposition with self-evaporated Fe catalysts in low-grade silica. We investigated the characteristics of the SiC nanowires, which were grown on a porous body with Ar flowing in a vacuum furnace. Their structural, optical, and electrical properties were analyzed with X-ray diffraction (XRD), transmission electron microscopy (TEM), and selective area electron diffraction (SAED). We obtained high-quality SiC single crystalline nanowire without stacking faults that may have uses in industrial applications.

• Vacuum Magazine
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• v.3 no.3
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• pp.15-18
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• 2016

In future wearable electronic systems, 3-dimensional (3D) devices have attracted much attention due to their high density integration and low-power functionality. Among 3D devices, gate-all-around (GAA) nanowire transistor provides superior gate controllability, resulting in suppressing short channel effect and other drawbacks in 2D metal-oxide-semiconductor field-effect transistor (MOSFET). Silicon nanowires (SiNWs) are the most promising building block for GAA structure device due to their compatibility with the current Si-based ultra large scale integration (ULSI) technology. Moreover, the theoretical limit for subthreshold swing (SS) of MOSFET is 60 mV/dec at room temperature, which causes the increase in Ioff current. To overcome theoretical limit for the SS, it is crucial that research into new types of device concepts should be performed. In our present studies, we have experimentally demonstrated feedback FET (FBFET) and tunnel FET (TFET) with sub-60 mV/dec based on SiNWs. Also, we fabricated SiNW based complementary TFET (c-TFET) and SiNW complementary metal-oxide-semiconductor (CMOS) inverter. Our research demonstrates the promising potential of SiNW electronic devices for future wearable electronic systems.

• Proceedings of the Korean Vacuum Society Conference
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• 2004.02a
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• pp.104-104
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• 2004