• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.11a
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• pp.165-166
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• 2012

표면의 젖음성은 어플리케이션의 매우 중요한 점으로, 이것은 표면에너지와 표면의 조도에 의해 결정된다. 표면의 젖음성을 낮추기 위하여 저온 PECVD 공정을 통해 초소수성 박막을 만들었다. $SiO_xC_yH_z$ 필름을 만들기 위하여 RF power을 사용하였고, HMDS (hexamethyl-disilazane) precursor과 함께 수소 기체를 통해 증착하였다. 이 실험에서는 수소와 RF power를 변수로 진행하였고, 이것은 소수성 박막의 표면에너지를 변화시켰다. 필름을 합성한 후 contact angle measurement 및 AFM을 사용해 표면에너지와 표면조도를 관찰하였다. 또한 필름의 화학적 결합을 알기 위해 FT-IR을 이용하였다. 여기에서 표면의 에너지는 표면의 조도와 화학적 결합상태에 의해서 영향을 받았음을 알 수 있었다.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.785-789
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• 2005

Low temperature deposition of silicon and silicon nitride films by catalytic CVD technique was studied for application to thin film transistors on plastic substrates for flexible AMOLEDs. The substrate temperature initially held at room temperature, and was controlled successfully below $150^{\circ}C$ during the entire deposition process. Amorphous silicon films having good adhesion, good surface morphology and sufficiently low content of atomic hydrogen were obtained and could be successfully crystallized using excimer laser without a prior dehydrogenation step. $SiN_x$ films showed a good refractive index, a high deposition rate, a moderate breakdown field and a dielectric constant. The Cat-CVD silicon and silicon nitride films can be good candidates for fabricating thin films transistors on plastic substrates to drive active-matrix organic light emitting display.

• Korean Journal of Optics and Photonics
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• v.22 no.2
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• pp.90-95
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• 2011

We propose a super-thin and light-weight liquid crystal cell, in which glass substrates are eliminated and polarizers are used as substrates. We fabricate a polarizer substrate by depositing a-SiOX as a buffer layer, indium-tin-oxide as a transparent conducting layer, and a-SiOX as an alignment layer on a polarizer sequentially at a low temperature. We use the ion-beam method to align liquid crystals on polarizer substrates.

• Journal of the Korean institute of surface engineering
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• v.39 no.6
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• pp.255-262
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• 2006

Pd-Cu alloy membrane for hydrogen separation was fabricated by sputtering and Cu reflow process. At first, the Pd and Cu was continuously deposited by sputtering method on oxidized Si support, the Cu reflow process was followed. Microstructure of the surface and permeability of the membrane was investigated depending on various reflow temperature, time, Pd/cu composition and supports. With respect to our result, Pd-Cu thin film (90 wt.% Pd/10 wt.% Cu) deposited by sputtering process with thickness of $2{\mu}m$ was heat-treated for Cu reflow The voids of the membrane surface were completely filled and the dense crystal surface was formed by Cu reflow behavior at $700^{\circ}C$ for 1 hour. Cu reflow process, which is adopted for our work, could be applied to fabrication of dense Pd-alloy membrane for hydrogen separation regardless of supports. Ceramic or metal support could be easily used for the membrane fabricated by reflow process. The Cu reflow process must result in void-free surface and dense crystalline of Pd-alloy membrane, which is responsible for improved selectivity oi the membrane.

• Transactions on Electrical and Electronic Materials
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• v.9 no.2
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• pp.47-51
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• 2008

In this paper, thermal stability of Nickel silicide formed on p-type silicon wafer using Ni-V alloy film was studied. As compared with pure Ni, Ni-V shows better thermal stability. The addition of Vanadium suppresses the phase transition of NiSi to $NiSi_2$ effectively. Ni-V single structure shows the best thermal stability compared with the other Ni-silicide using TiN and Co/TiN capping layers. To enhance the thermal stability up to $650^{\circ}C$ and find out the optimal thickness of Ni silicide, different thickness of Ni-V was also investigated in this work.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1646-1648
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• 2000

This paper investigated structural and electrical properties of $Y_{2}O_3$ as a buffer layer of sin91r transistor FRAM (ferroelectric RAM). $Y_{2}O_3$ buffer layers were deposited at a low substrate temperature below 400$^{\circ}C$ and then RTA (rapid thermal anneal) treated. Investigated parameters are substrate temperature, $O_2$ partial pressure, post- annealing temperature, and suppression of interfacial $SiO_2$ layer generation. for a well-fabricated sample, we achieved that leakage current density ($J_{leak}$) in the order of $10^{-7}A/cm2$, breakdown electric field ($E_{br}$) about 2 MV/cm for $Y_{2}O_3$ film. Capacitance versus voltage analysis illustrated dielectric constants of 7.47. We successfully achieved an interface state density of $Y_{2}O_3$/Si as low as $8.72{\times}10^{10}cm^{-2}eV^{-1}$. The low interface states were obtained from very low lattice mismatch less than 1.75%.

• Journal of Electrical Engineering and Technology
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• v.2 no.1
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• pp.98-101
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• 2007

Yttrium(Y)-substituted bismuth titanate $(Bi_{4-x},Y_x)Ti_3O_{12}$ [x=0, 0.25, 0.5, 0.75, 1](BYT) thin films were deposited using an RF sputtering method on the $Pt/TiO_2/SiO_2/Si$ substrates. The structural properties and electrical properties of yttrium-substituted $(Bi_4-xYx)Ti_3O_{12}$ thin films were analyzed. The remanent polarization of $(Bi_4-xYx)Ti_3O_{12}$ films increased with increasing Y-content. The $(Bi_{3.25}Y_{0.75})Ti_3O_{12}$ films fabricated using a top Au electrode showed saturated polarization-electric field(P-E) switching curves with a remanent polarization(Pr) of $8{\mu}C/cm^2$ and coercive field (Ec) of 53 kV/cm at an applied voltage of 7 V. The $(Bi_{3.25}Y_{0.75})Ti_3O_{12}$ films exhibited fatigue-free behavior up to $4.5{\times}10^{11}$ read/write switching cycles at a frequency of 1MHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.472-473
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• 2007

The $(Sr_{1-x}Ca_x)TiO_3$(ST) thin films are deposited on Pt-coated electrode(Pt/TiN/$SiO_2$/Si) using RF sputtering method with substitutional contents of Ca. The maximum grain of thin films is obtained by substitution of Ca at 15[mol%]. Also, the composition of ST thin films were closed to stoichiometry(1.081~1.117 in A/B ratio). The dielectric constant changes almost linearly in temperature ranges of -80~+90[$^{\circ}C$]. The current-voltage characteristics of ST15 thin films showed the increasing leakage current as the measuring temperature increases.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.36-37
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• 2006

Titanium oxy-nitride ($TiN_O_y$) thin films were deposited on $SiO_2$/Si substrates using reactive dc magnetron sputtering, and were then annealed at various temperatures in air ambient to incorporate oxygen into the films. The effect of annealing temperature on the structural and electrical properties of the films was investigated. The grain size of the films decreases with increasing annealing temperature. On the other hand, crystallinity of the films is independent of annealing temperature in air ambient. Resistivity of the films increases remarkably as an annealing temperature increases and temperature coefficience of resistance (TCR) of the films varies from a positive value to a negative value. The films annealed at $350^{\circ}C$ for 30 min exhibited a near-zero TCR value of approximately -5 ppm/K. The decrease of the grain size with increasing annealing temperature was attributed to an increase of oxygen concentration incorporated into the films during anncaling treatment.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.151-151
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• 2010

In this paper, the electrically properties of nonvolatile memory (NVM) using multi-stacks gate insulators of oxide-nitride-oxynitride (ONOn) and active layer of the low temperature polycrystalline silicon (LTPS) were investigated. From hydrogenated amorphous silicon (a-Si:H), the LTPS thin films with high crystalline fraction of 96% and low surface's roughness of 1.28 nm were fabricated by the metal induced crystallization (MIC) with annealing conditions of $650^{\circ}C$ for 5 hours on glass substrates. The LTPS thin film transistor (TFT) or the NVM obtains a field effect mobility of ($\mu_{FE}$) $10\;cm^2/V{\cdot}s$, threshold voltage ($V_{TH}$) of -3.5V. The results demonstrated that the NVM has a memory window of 1.6 V with a programming and erasing (P/E) voltage of -14 V and 14 V in 1 ms. Moreover, retention properties of the memory was determined exceed 80% after 10 years. Therefore, the LTPS fabricated by the MIC became a potential material for NVM application which employed for the system integration of the panel display.