• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.4
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• pp.344-349
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• 2006

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. We aimed to systematically investigate the dependence of SiC epilayer quality and growth rate during the sublimation growth using the CST method on various process parameters such as the growth temperature and working pressure. The etched surface of a SiC epitaxial layer grown with low growth rate $(30{\mu}m/h)$ exhibited low etch pit density (EPD) of ${\sim}2000/cm^2$ and a low micropipe density (MPD) of $2/cm^2$. The etched surface of a SiC epitaxial layer grown with high growth rate (above $100{\mu}m/h$) contained a high EPD of ${\sim}3500/cm^2$ and a high MPD of ${\sim}500/cm^2$, which indicates that high growth rate aids the formation of dislocations and micropipes in the epitaxial layer. We also investigated the Schottky barrier diode (SBD) characteristics including a carrier density and depletion layer for Ni/SiC structure and finally proposed a MESFET device fabricated by using selective epilayer process.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.7 no.2
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• pp.197-206
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• 1997

A SiC epilayer on the 6H-SiC crystal substrate was grown by chemical vapor deposition (CVD). The crystal structure of the SiC epilayer was investigated by using the X-ray diffraction patterns and the Roman scattering spectroscopy. The SiC epilayer on the 6H-SiC substrate was grown to be homoepilayer by CVD. In order to distinguish a certain SiC polytype mixed in the SiC crystal grown by the modified Lely method, we have calculated the X-ray diffraction intensities and Brags angles of the typical SiC crystal powders. By comparing the measured X-ray diffraction pattern with the calculated ones, it was identified that the SiC crystal grown by the modified Lely method was the 6H-SiC crystal mixed some 15R-SiC.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1997.10a
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• pp.141-144
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• 1997

High quality 3C-SiC epilayer was grown on Si(111) at 125$0^{\circ}C$ using chemical vapor deposition(CVD) technique by pyrolyzing tetramethylsilane(TMS). 3C-SiC epilayer was doped by tetramethylgallium(TMGa) during the CVD growth. The crystallinity of 3C-SiC was significantly enhanced by doping the gallium impurity.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.10
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• pp.767-770
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• 2010

In this work, we investigated the static characteristics of 4H-SiC vertical metal-oxidesemiconductor field effect transistors (VMOSFETs) by adjusting the doping level of n-epilayer and the effect of a current spreading layer (CSL), which was inserted below the p-base region with highly doped n+ state ($5{\times}10^{17}cm^{-3}$). The structure of SiC VMOSFET was designed by using a 2-dimensional device simulator (ATLAS, Silvaco Inc.). By varying the n-epilayer doping concentration from $1{\times}10^{16}cm^{-3}$ to $1{\times}10^{17}cm^{-3}$, we investigated the static characteristics of SiC VMOSFETs such as blocking voltages and on-resistances. We found that CSL helps distribute the electron flow more uniformly, minimizing current crowding at the top of the drift region and reducing the drift layer resistance. For that reason, silicon carbide VMOSFET structures of highly intensified blocking voltages with good figures of merit can be achieved by adjusting CSL and doping level of n-epilayer.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.30 no.3
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• pp.96-102
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• 2020

In this paper, AlN epilayers on 6H-SiC (0001) substrate are grown by mixed source hydride vapor phase epitaxy (MS-HVPE). AlN epilayer of 0.5 ㎛ thickness was obtained with a growth rate of 5 nm per hour. The surface of AlN epilayer grown on 6H-SiC (0001) substrate was investigated by field emission scanning electron microscopy (FE-SEM) and energy dispersive X-ray spectroscopy (EDS). Dislocation density was considered through HR-XRD and related calculations. A fine crystalline AlN epilayer with screw dislocation density of 1.4 × 10⁹ cm^-2 and edge dislocation density of 3.8 × 10⁹ cm^-2 was confirmed. The AlN epilayer on 6H-SiC (0001) substrate grown by using the mixed source HVPE method could be applied to power devices.

• Journal of Korean Vacuum Science & Technology
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• v.6 no.2
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• pp.84-87
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• 2002

The Si$_{1-x}$ Gex/Si surface alloy (x = 0.3, 0.4 and 0.5), which are prepared by solid source MBE and have the SiGe epilayer thickness of 50$\AA$, are annealed with different parameters. The surface structure analyses of the heterostructure samples are made on a triple-axis X-ray diffractometer in grazing incidence X-ray diffraction (GIXRD) geometry. It has been found that with different annealing time (1.5h, 18h, 64h) and annealing temperature (550 $^{\circ}C$, 750 $^{\circ}C$), the SiGe epilayer experienced different strain relaxation process, which was deduced from the GIXRD measurements of the in-plane (220) diffraction peak of Si(001) substrate and the relevant (220) surface diffraction of SiGe epilayer. The results show that the stress relieving and the lateral strain relaxation in the SiGe/Si heterostructure can be promoted by correct annealing, which is very helpful for the preparation of SiGe/Si strained superlattice with fine strain crystallization..

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.350-353
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• 2002

High voltage SiC Schottky barrier diodes with field plate structure have been fabricated and characterized. N-type 4H-SiC wafer with an epilayer of ∼10$\^$15/㎤ doping level was used as a starting material. Various Schottky metals such as Ni, Pt, Ta, Ti were sputtered and thermally-evaporated on the low-doped epilayer. Ohmic contact was formed at the backside of the SiC wafer by annealing at 950$^{\circ}C$ for 90 sec in argon using rapid thermal annealer. Field oxide of 550${\AA}$ in thickness was formed by a wet oxidation process at l150$^{\circ}C$ for 3h and subsequently heat-treated at l150$^{\circ}C$ for 30 min in argon for improving oxide quality. The turn-on voltages of the Ni/4H-SiC Schottky diode was 1.6V which was much higher than those of Pt(1.0V), Ta(0.7V) and Ti(0.7). The voltage drop was measured at the current density of 100A/$\textrm{cm}^2$ showing 2.1V for Ni Schottky diode, 1.45V for Pt 1.35V, for Ta, and 1.25V for Ti, respectively. The maximum reverse breakdown voltage was measured 1100V in the file plated Schottky diodes with 101an thick epilayer.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.9 no.3
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• pp.273-279
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• 1999

The home-made hot wall epitaxy (HWE) system was utilized for GaN epitaxial layer growth on the Si(001) substrate. It was appeared that GaN epilayer grow with mixed phase of Zinc blende and Wurtzite structure from photoluminescence (PL) and x-ray diffraction (XRD) analysis at the room temperature. We found that intial growth layer has Wurtzite structure from photoluminescence (PL) and x-ray diffractio (XRD) analyses at the room temperature. Wefound that initial growth layer has Wurtzite structure when initial deposition time, the temperature of substrate and source are 4 min, $720^{\circ}C$ and $860^{\circ}C$ respectively, and at the epi growth process GaN, epilayer was grown with relatively stable Wurtzite structure when the temperature of substrate and source are $1020^{\circ}C$ and $910^{\circ}C$ respectively.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.33 no.2
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• pp.45-53
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• 2023

The growth of Si on 4H-SiC substrate has a wide range of applications as a very useful material in power semiconductors, bipolar junction transistors and optoelectronics. However, it is considerably difficult to grow very fine crystalline Si on 4H-SiC owing to the lattice mismatch of approximately 20 % between Si and 4H-SiC. In this paper, we report the growth of a Si epilayer by an Al-related nanostructure cluster grown on a 4H-SiC substrate using a mixed-source hydride vapor phase epitaxy (HVPE) method. In order to grow hexagonal Si on the 4H-SIC substrate, we observed the process in which an Al-related nanostructure cluster was first formed and an epitaxial layer was formed by absorbing Si atoms. From the FE-SEM and Raman spectrum results of the Al-related nanostructure cluster and the hexagonal Si epitaxial layer, it was considered that the hexagonal Si epitaxial layer had different characteristics from the general cubic Si structure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.12
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• pp.1056-1061
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• 2007

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. In this study, we aimed to systematically investigate surface morphologies and electrical properties of SiC epitaxial layers grown with varying a SiC/Al ratio in a SiC source powder during the sublimation growth using the CST method. The surface morphology was dramatically changed with varying the SiC/Al ratio. When the SiC/Al ratio of 90/1 was used, the step bunching was not observed in this magnification and the ratio of SiC/Al is an optimized range to grow of p-type SiC epitaxial layer. It was confirmed that the acceptor concentration of epitaxial layer was continuously decreased with increasing the SiC/Al ratio. 4H-SiC MESFETs haying a micron-gate length were fabricated using a lithography process and their current-voltage performances were characterized. It was confirmed that the increase of the negative voltage applied on the gate reduced the drain current, showing normal operation of FET device.