• 한국전기전자재료학회논문지
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• 제19권4호
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• pp.344-349
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• 2006

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. We aimed to systematically investigate the dependence of SiC epilayer quality and growth rate during the sublimation growth using the CST method on various process parameters such as the growth temperature and working pressure. The etched surface of a SiC epitaxial layer grown with low growth rate $(30{\mu}m/h)$ exhibited low etch pit density (EPD) of ${\sim}2000/cm^2$ and a low micropipe density (MPD) of $2/cm^2$. The etched surface of a SiC epitaxial layer grown with high growth rate (above $100{\mu}m/h$) contained a high EPD of ${\sim}3500/cm^2$ and a high MPD of ${\sim}500/cm^2$, which indicates that high growth rate aids the formation of dislocations and micropipes in the epitaxial layer. We also investigated the Schottky barrier diode (SBD) characteristics including a carrier density and depletion layer for Ni/SiC structure and finally proposed a MESFET device fabricated by using selective epilayer process.

• 한국결정성장학회지
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• 제7권2호
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• pp.197-206
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• 1997

6H-SiC 위에 SiC 에피층이 화학 기상 증착(CVD)에 의하여 성장되었다. 성장된 SiC 에피층의 결정구조는 X-선 회절과 Raman 분광을 사용하여 조사되었으며, 이 에피층은 6H-SiC로서 성장되었음을 확인하였다. 수정된 Lely법으로 성장된 한 SiC 결정 분말의 결정구조를 확인하기 위하여 전형적인 SiC polytype들의 X-선 회절상을 계산하였으며, 측정된 X-선 회절상과 비교하여 이 SiC 결정에는 15R-SiC가 약간 혼재되어 있음을 확인하였다.

• 한국결정성장학회:학술대회논문집
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• 한국결정성장학회 1997년도 Proceedings of the 13th KACG Technical Meeting `97 Industrial Crystallization Symposium(ICS)-Doosan Resort, Chunchon, October 30-31, 1997
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• pp.141-144
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• 1997

High quality 3C-SiC epilayer was grown on Si(111) at 125$0^{\circ}C$ using chemical vapor deposition(CVD) technique by pyrolyzing tetramethylsilane(TMS). 3C-SiC epilayer was doped by tetramethylgallium(TMGa) during the CVD growth. The crystallinity of 3C-SiC was significantly enhanced by doping the gallium impurity.

• 한국전기전자재료학회논문지
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• 제23권10호
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• pp.767-770
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• 2010

In this work, we investigated the static characteristics of 4H-SiC vertical metal-oxidesemiconductor field effect transistors (VMOSFETs) by adjusting the doping level of n-epilayer and the effect of a current spreading layer (CSL), which was inserted below the p-base region with highly doped n+ state ($5{\times}10^{17}cm^{-3}$). The structure of SiC VMOSFET was designed by using a 2-dimensional device simulator (ATLAS, Silvaco Inc.). By varying the n-epilayer doping concentration from $1{\times}10^{16}cm^{-3}$ to $1{\times}10^{17}cm^{-3}$, we investigated the static characteristics of SiC VMOSFETs such as blocking voltages and on-resistances. We found that CSL helps distribute the electron flow more uniformly, minimizing current crowding at the top of the drift region and reducing the drift layer resistance. For that reason, silicon carbide VMOSFET structures of highly intensified blocking voltages with good figures of merit can be achieved by adjusting CSL and doping level of n-epilayer.

• 한국결정성장학회지
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• 제30권3호
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• pp.96-102
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• 2020

본 논문에서는 6H-SiC (0001) 기판 위에 AlN 에피층을 혼합 소스 수소화물 기상 에피택시 방법에 의해 성장하였다. 시간당 5 nm의 성장률로 0.5 ㎛ 두께의 AlN 에피층을 얻었다. FE-SEM과 EDS 결과를 통해 6H-SiC (0001) 기판 위에 성장된 AlN 에피층 표면을 조사하였다. HR-XRD와 계산식을 통해 전위 밀도를 예측하였다. 1.4 × 10⁹ cm^-2의 나사 전위 밀도와 3.8 × 10⁹ cm^-2의 칼날 전위 밀도를 가지는 우수한 결정질의 AlN 에피층을 확인하였다. 혼합소스 HVP E 방법에 의해 성장된 6H-SiC 기판 위의 AlN 에피층은 전력소자 등에 응용이 가능할 것으로 판단된다.

• Journal of Korean Vacuum Science & Technology
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• 제6권2호
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• pp.84-87
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• 2002

The Si$_{1-x}$ Gex/Si surface alloy (x = 0.3, 0.4 and 0.5), which are prepared by solid source MBE and have the SiGe epilayer thickness of 50$\AA$, are annealed with different parameters. The surface structure analyses of the heterostructure samples are made on a triple-axis X-ray diffractometer in grazing incidence X-ray diffraction (GIXRD) geometry. It has been found that with different annealing time (1.5h, 18h, 64h) and annealing temperature (550 $^{\circ}C$, 750 $^{\circ}C$), the SiGe epilayer experienced different strain relaxation process, which was deduced from the GIXRD measurements of the in-plane (220) diffraction peak of Si(001) substrate and the relevant (220) surface diffraction of SiGe epilayer. The results show that the stress relieving and the lateral strain relaxation in the SiGe/Si heterostructure can be promoted by correct annealing, which is very helpful for the preparation of SiGe/Si strained superlattice with fine strain crystallization..

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.350-353
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• 2002

High voltage SiC Schottky barrier diodes with field plate structure have been fabricated and characterized. N-type 4H-SiC wafer with an epilayer of ∼10$\^$15/㎤ doping level was used as a starting material. Various Schottky metals such as Ni, Pt, Ta, Ti were sputtered and thermally-evaporated on the low-doped epilayer. Ohmic contact was formed at the backside of the SiC wafer by annealing at 950$^{\circ}C$ for 90 sec in argon using rapid thermal annealer. Field oxide of 550${\AA}$ in thickness was formed by a wet oxidation process at l150$^{\circ}C$ for 3h and subsequently heat-treated at l150$^{\circ}C$ for 30 min in argon for improving oxide quality. The turn-on voltages of the Ni/4H-SiC Schottky diode was 1.6V which was much higher than those of Pt(1.0V), Ta(0.7V) and Ti(0.7). The voltage drop was measured at the current density of 100A/$\textrm{cm}^2$ showing 2.1V for Ni Schottky diode, 1.45V for Pt 1.35V, for Ta, and 1.25V for Ti, respectively. The maximum reverse breakdown voltage was measured 1100V in the file plated Schottky diodes with 101an thick epilayer.

• 한국결정성장학회지
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• 제9권3호
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• pp.273-279
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• 1999

Si(001)을 기판으로 한 GaN 박막을 성장하기 위하여 hot wall epitaxy(HWE) 장치를 자체 제작하였다. HWE 장치를 이용하여 Si(001) 기판 위에 GaN 박막에 대한 상온에서의 광 발광(PL) 측정에서 GaN 초기층 성장온도가 $700^{\circ}C$ 보다 낮은 온도 조건에서 성장된 GaN 박막이 Zinc blende 구조와 Wurzite 구조가 혼합되어 성장되어지는 것으로 추측되며, $700^{\circ}C$ 이상의 온도에서는 성장된 GaN 박막이 주로 wurtzite 구조로 성장된다는 것을 알 수 있다. 그리고 x-선 회절 측정으로부터 성장한 GaN 박막이 Zinc blende와 Wurtzite의 두가지 구조가 혼합된 형태로 성장되었다는 것을 알 수 있었다. GaN 박막을 성장하기 위한 조건에서 초기층 성장조건은 증발부의 온도 $860^{\circ}C$와 기판부의 온도가 $720^{\circ}C$ 근처에서 4분동안 성장하였을 때 Wurtzite의 특성을 보이며, GaN 박막의 성장조건은 기판부의 온도 $1020^{\circ}C$, 증발부의 온도 $910^{\circ}C$에서 그리고 Ammonia gas의 유량을 120 sccm으로 하였을 때 보다 안정한 Wurtzite 구조특성을 보이게 되었다.

• 한국결정성장학회지
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• 제33권2호
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• pp.45-53
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• 2023

4H-SiC 기판 위의 Si 성장은 전력 반도체, 바이폴라 접합 트랜지스터 및 광전자 공학에서 매우 유용한 재료로서 광범위한 응용 분야를 가지고 있다. 그러나 Si와 4H-SiC 사이에 약 20 %의 격자 불일치로 인해 4H-SiC에서 매우 양질의 결정 Si를 성장시키는 것은 상당히 어렵다. 본 논문에서는 혼합 소스 수소화물 기상 에피택시 방법을 이용하여 4H-SiC 기판에서 성장한 Al 관련 나노 구조체 클러스터에 의한 육각형 Si 에피층의 성장을 보고한다. 4H-SiC 기판 위에 육각형 Si 에피층을 성장시키기 위해 먼저 Al 관련 나노 구조체 클러스터가 형성되고 Si 원자를 흡수하여 육각형 Si 에피층이 형성되는 과정을 관찰하였다. Al 관련 나노 구조체 클러스터와 육각형 Si 에피층에 대하여 FE-SEM 및 라만 스펙트럼 결과로부터 육각형 Si 에피층은 일반적인 입방정계 Si 구조와 다른 특성을 가지는 것으로 판단된다.

• 한국전기전자재료학회논문지
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• 제20권12호
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• pp.1056-1061
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• 2007

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. In this study, we aimed to systematically investigate surface morphologies and electrical properties of SiC epitaxial layers grown with varying a SiC/Al ratio in a SiC source powder during the sublimation growth using the CST method. The surface morphology was dramatically changed with varying the SiC/Al ratio. When the SiC/Al ratio of 90/1 was used, the step bunching was not observed in this magnification and the ratio of SiC/Al is an optimized range to grow of p-type SiC epitaxial layer. It was confirmed that the acceptor concentration of epitaxial layer was continuously decreased with increasing the SiC/Al ratio. 4H-SiC MESFETs haying a micron-gate length were fabricated using a lithography process and their current-voltage performances were characterized. It was confirmed that the increase of the negative voltage applied on the gate reduced the drain current, showing normal operation of FET device.