• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.111-111
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• 2007

Further scaling the semiconductor devices down to low dozens of nanometer needs the extremely shallow depth in junction and the intentional counter-doping in the silicon gate. Conventional ion beam ion implantation has some disadvantages and limitations for the future applications. In order to solve them, therefore, plasma source ion implantation technique has been considered as a promising new method for the high throughputs at low energy and the fabrication of the ultra-shallow junctions. In this paper, we study about the effects of DC bias and base pressure as a process parameter. The diluted mixture gas (5% $PH_3/H_2$) was used as a precursor source and chamber is used for vacuum pressure conditions. After ion doping into the Si wafer(100), the samples were annealed via rapid thermal annealing, of which annealed temperature ranges above the $950^{\circ}C$. The junction depth, calculated at dose level of $1{\times}10^{18}/cm^3$, was measured by secondary ion mass spectroscopy(SIMS) and sheet resistance by contact and non-contact mode. Surface morphology of samples was analyzed by scanning electron microscopy. As a result, we could accomplish the process conditions better than in advance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.408-409
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• 2007

Al-doped p-type ZnO films were fabricated on n-Si (100) and homo-buffer layers in pure oxygen at $450^{\circ}C$ by RF magnetron sputtering. Target was ZnO ceramic mixed with 2wt% $Al_2O_3$. XRD spectra show that the Al-doped ZnO thin films have ZnO crystal structure and homo-buffer layers are beneficial to Al-doped ZnO films to grow along c-axis. Hall Effect experiments with Van der Pauw configuration show that p-type carrier concentrations are ranged from $1.66{\times}10^{16}\;to\;4.04{\times}10^{18}cm^{-3}$, mobilities from 0.194 to $2.3cm^2V^{-1}s^{-1}$ and resistivities from 7.97 to $18.4{\Omega}cm$. P-type sample has density of $5.40cm^{-3}$ which is smaller than theoretically calculated value of $5.67cm^{-3}$. XPS spectra show that O1s has O-O and Zn-O structures and A12p has only Al-O structure. P-ZnO:Al/n-ZnO:Al junctions were fabricated by magnetron sputtering. V-I curves show that the p-n junctions have rectifying characteristics.

• Korean Journal of Materials Research
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• v.25 no.3
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• pp.138-143
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• 2015

Aluminum nitride, a compound semiconductor, has a Wurtzite structure; good material properties such as high thermal conductivity, great electric conductivity, high dielectric breakdown strength, a wide energy band gap (6.2eV), a fast elastic wave speed; and excellent in thermal and chemical stability. Furthermore, the thermal expansion coefficient of the aluminum nitride is similar to those of Si and GaAs. Due to these characteristics, aluminum nitride can be applied to electric packaging components, dielectric materials, SAW (surface acoustic wave) devices, and photoelectric devices. In this study, we surveyed the crystallization and preferred orientation of AlN thin films with an X-ray diffractometer. To fabricate the AlN thin film, we used the magnetron sputtering method with $N_2$, NH3 and Ar. According to an increase in the partial pressures of $N_2$ and $NH_3$, Al was nitrified and deposited onto a substrate in a molecular form. When AlN was fabricated with $N_2$, it showed a c-axis orientation and tended toward a high orientation with an increase in the temperature. On the other hand, when AlN was fabricated with $NH_3$, it showed a-axis orientation. This result is coincident with the proposed mechanism. We fabricated AlN thin films with an a-axis orientation by controlling the sputtering electric power, $NH_3$ pressure, deposition speed, and substrate temperature. According to the proposed mechanism, we also fabricated AlN thin films which demonstrated high a-axis and c-axis orientations.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.11-11
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• 2010

Thin-film-transistors (TFTs) that can be deposited at low temperature have recently attracted lots of applications such as sensors, solar cell and displays, because of the great flexible electronics and transparent. Transparent and flexible transistors are being required that high mobility and large-area uniformity at low temperature [1]. But, unfortunately most of TFT structures are used to be $SiO_2$ as gate dielectric layer. The $SiO_2$ has disadvantaged that it is required to high driving voltage to achieve the same operating efficiency compared with other high-k materials and its thickness is thicker than high-k materials [2]. To solve this problem, we find lots of high-k materials as $HfO_2$, $ZrO_2$, $SiN_x$, $TiO_2$, $Al_2O_3$. Among the High-k materials, $Al_2O_3$ is one of the outstanding materials due to its properties are high dielectric constant ( ~9 ), relatively low leakage current, wide bandgap ( 8.7 eV ) and good device stability. For the realization of flexible displays, all processes should be performed at very low temperatures, but low temperature $Al_2O_3$ grown by sputtering showed deteriorated electrical performance. Further decrease in growth temperature induces a high density of charge traps in the gate oxide/channel. This study investigated the effect of growth temperatures of ALD grown $Al_2O_3$ layers on the TFT device performance. The ALD deposition showed high conformal and defect-free dielectric layers at low temperature compared with other deposition equipments [2]. After ITO was wet-chemically etched with HCl : $HNO_3$ = 3:1, $Al_2O_3$ layer was deposited by ALD at various growth temperatures or lift-off process. Amorphous InGaZnO channel layers were deposited by rf magnetron sputtering at a working pressure of 3 mTorr and $O_2$/Ar (1/29 sccm). The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. The TFT devices were heat-treated in a furnace at $300^{\circ}C$ and nitrogen atmosphere for 1 hour by rapid thermal treatment. The electrical properties of the oxide TFTs were measured using semiconductor parameter analyzer (4145B), and LCR meter.

• KIEE International Transactions on Electrophysics and Applications
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• v.12C no.4
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• pp.208-213
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• 2002

The present study describe the electrical performance of amorphous T $a_2$ $O_{5-X}$ fabricated on the buffer layers Ti and Ti $O_2$. T $a_2$ $O_{5-X}$ thin films were grown on the Ti and Ti $O_2$ layers as a capacitor layer using reactive sputtering method. The X-ray pattern analysis indicated that the two as-deposited films were amorphous and the amorphous state was kept stable on the RTA(rapid thermal annealing) at even $700^{\circ}C$. Measurements of dielectric properties of the reactive sputtered T $a_2$ $O_{5-X}$ thin films fabricated in two simple MIS(metal insulator semiconductor), structures, (Cu/T $a_2$ $O_{5}$ Ti/Si and CuT $a_2$ $O_{5}$ Ti $O_2$Si) show that the amorphous T $a_2$ $O_{5}$ grown on Ti showed high dielectric constant (23～39) and high leakage current density(10$^{-3}$ ～10$^{-4}$ (A/$\textrm{cm}^2$)), whereas relatively low dielectric constant (～15) and tow leakage current density(10$^{-9}$ ～10$^{-10}$ (A/$\textrm{cm}^2$)) were observed in the amorphous T $a_2$ $O_{5}$ deposited on the Ti $O_2$ layer. The electrical behaviors of the T $a_2$ $O^{5}$ thin films were attributed to the contribution of Ti- $O_2$ and the compositionally gradient Ta-Ti-0, being the low dielectric layer and high leakage current barrier. In additional, The T $a_2$ $O_{5}$ Ti $O_2$ thin films exhibited dominant conduction mechanism contributed by the Poole-Frenkel emission at high electric field. In the case of T $a_2$ $O_{5}$ Ti $O_2$ thin films were related to the diffusion of Ta, Ti and O, followed by the creation of vacancies, in the rapid thermal treated thin films.films.

• Journal of IKEEE
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• v.11 no.4
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• pp.152-157
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• 2007

AlGaN/GaN high electron mobility transistors (HEMTs) were fabricated and the effect of ${N_2}O$ plasma on the electrical characteristics of the devices was investigated. The HEMT exposed to ${N_2}O$ plasma formed by 40 W of RF power in a chamber with pressure of 20 mTorr at a temperature of $200^{\circ}C$, exhibited a reduction of gate leakage current from 246 nA to 1.2 pA by 10 seconds treatment. The current between the two isolated active regions reduced from 3 uA to 7 nA and the sheet resistance of the active layer was lowered also. The variations of electrical characteristics for HEMT were occurred within a short time expose of 10 seconds and the successive expose did not influence on the improvements of gate leakage characteristics and conductivity of the active region. The reduced leakage current level was not varied by successive $SiO_2$ deposition and its removal. The transconductnace and drain current of AlGaN/GaN HEMTs were increased also by the expose to the ${N_2}O$ plasma.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.348-348
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• 2014

차세대 디스플레이 구동 회로 소자를 위한 재료로서, Amorphous Oxide Semiconductor (AOS)가 주목받고 있다. AOS는 기존의 Amorphous Silicon과 비교하여 뛰어난 이동도를 가지고 있으며, 넓은 밴드 갭에 의한 투명한 광학적 특성을 가지고 있다. 이러한 장점을 이용하여, AOS 박막은 thin film transistor (TFT)의 active channel로 이용 되고 있다. 하지만, AOS를 이용한 TFT의 경우, 시간이 경과함에 따라 $O_2$ 및 $H_2O$ 흡착에 의해 전기적 특성이 변하는 현상이 있다. 이러한 현상은 소자의 신뢰성에 있어 중요한 문제가 된다. 이러한 문제를 연구하기 위해 본 논문에서는, AOS 박막을 이용하여 bottom 게이트형 TFT를 제작하였다. 이를 위해 먼저, p-type Si 위에 건식산화방식으로 $SiO_2$(100 nm)를 성장시켜 게이트 산화막으로 이용하였다. 그리고 Zn과 Sn이 1: 2의 조성비를 가진 ZnSnO (ZTO) 용액을 제조한 후, 게이트 산화막 위에 spin coating 하였다. Splin coating된 용액에 남아 있는 솔벤트를 제거하기 위해 10분 동안 $230^{\circ}C$로 열처리를 한 후, 포토리소그래피와 에칭 공정을 이용하여 ZTO active channel을 형성하였다. 그 후, 박막 내에 남아 있는 불순물을 제거하고 ZTO TFT의 전기적인 특성을 향상시키기 위하여, $600^{\circ}C$의 열처리를 30분 동안 진행 하여 junctionless형 TFT 제작을 완료 하였다. 제작된 소자의 시간 경과에 따른 열화를 확인하기 위하여, 대기 중에서 2시간마다 HP-4156B 장비를 이용하여 전기적인 특성을 확인 하였으며, 이러한 열화는 후처리 공정을 통하여 회복시킬 수 있었다. 열화의 회복을 위한 후처리 공정으로, 퍼니스를 이용한 고온에서의 열처리와 microwave를 이용하여 저온 처리를 이용하였다. 결과적으로, TFT는 소자가 제작된 이후, 시간에 경과함에 따라서 on/off ratio가 감소하여 열화되는 경향을 보여 주었다. 이러한 현상은, TFT 소자의 ZTO back-channel에 대기 중에 있는 $O_2$ 및 $H_2O$의 분자의 물리적인 흡착으로 인한 것으로 보인다. 그리고 추가적인 후처리 공정들에 통해서, 다시 on/off ratio가 회복 되는 현상을 확인 하였다. 이러한 추가적인 후처리 공정은, 열화된 소자에 퍼니스에 의한 고온에서의 장시간 열처리, microwave를 이용한 저온에서 장시간 열처리, 그리고 microwave를 이용한 저온에서의 단 시간 처리를 수행 하였으며, 모든 소자에서 성공적으로 열화 되었던 전기적 특성이 회복됨을 확인 할 수 있었다. 이러한 결과는, 저온임에도 불구하고, microwave를 이용함으로 인하여, 물리적으로 흡착된 $O_2$ 및 $H_2O$가 짧은 시간 안에 ZTO TFT의 back-channel로부터 탈착이 가능함과 동시에 소자의 특성을 회복 가능 함 의미한다.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.200-200
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• 2010

In recent times, metal oxide semiconductors thin films transistor (TFT), such as zinc and indium based oxide TFTs, have attracted considerable attention because of their several advantageous electrical and optical properties. There are many deposition methods for fabrication of ZnO-based materials such as chemical vapor deposition, RF/DC sputtering and pulsed laser deposition. However, these vacuum process require expensive equipment and result in high manufacturing costs. Also, the methods is difficult to fabricate various multicomponent oxide semiconductor. Recently, several groups report solution processed metal oxide TFTs for low cost and non vacuum process. In this study, we have newly developed solution-processed TFTs based on Ti-related multi-component transparent oxide, i. e., InTiO as the active layer. We propose new multicomponent oxide, Titanium indium oxide(TiInO), to fabricate the high performance TFT through the sol-gel method. We investigated the influence of relative compositions of Ti on the electrical properties. Indium nitrate hydrate [$In(NO^3).xH_2O$] and Titanium isobutoxide [$C_{16}H_{36}O_4Ti$] were dissolved in acetylacetone. Then monoethanolamine (MEA) and acetic acid ($CH_3COOH$) were added to the solution. The molar concentration of indium was kept as 0.1 mol concentration and the amount of Ti was varied according to weighting percent (0, 5, 10%). The complex solutions become clear and homogeneous after stirring for 24 hours. Heavily boron (p+) doped Si wafer with 100nm thermally grown $SiO_2$ serve as the gate and gate dielectric of the TFT, respectively. TiInO thin films were deposited using the sol-gel solution by the spin-coating method. After coating, the films annealed in a tube furnace at $500^{\circ}C$ for 1hour under oxygen ambient. The 5% Ti-doped InO TFT had a field-effect mobility $1.15cm^2/V{\cdot}S$, a threshold voltage of 4.73 V, an on/off current ratio grater than $10^7$, and a subthreshold slop of 0.49 V/dec. The 10% Ti-doped InO TFT had a field-effect mobility $1.03\;cm^2/V{\cdot}S$, a threshold voltage of 1.87 V, an on/off current ration grater than $10^7$, and a subthreshold slop of 0.67 V/dec.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.32 no.4
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• pp.121-127
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• 2022

β-Gallium oxide (Ga₂O₃), an ultra-wide bandgap semiconductor, has attracted great attention due to its promising applications for high voltage power devices. The most stable phase among five different polytypes, β-Ga₂O₃ has the wider bandgap of 4.9 eV and higher breakdown electric field of 8 MV/cm. Furthermore, it can be grown from melt source, implying higher growth rate and lower fabrication cost than other wide bandgap semiconductors such as SiC, GaN and diamond for the power device applications. In this study, β-Ga₂O₃ bulk crystals were grown by the edge-defined film-fed growth (EFG) process. The growth direction and the principal surface were set to be the [010] direction and the (100) plane of the β-Ga₂O₃ crystal, respectively. The spectra measured by Raman an alysis could exhibit the crystal phase an d impurity dopin g in the β-Ga₂O₃ ingot, and the crystallinity quality and crystal direction were analyzed using high-resolution X-ray diffraction (HRXRD). The crystal quality and various properties of as-grown β-Ga₂O₃ ribbon was systematically analyzed in order to investigate the spatial variation in entire crystal grown by EFG method.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.34 no.4
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• pp.109-116
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• 2024

β-Ga₂O₃ is a representative ultra-wide bandgap (UWBG) semiconductor that has attracted much attention for power device applications due to its wide-bandgap of 4.9 eV and high-breakdown voltage of 8 MV/cm. In addition, because solution growth is possible, it has advantages such as fast growth rate and lower production cost compared to SiC and GaN [1-2]. In this study, we have successfully grown Si-doped 10 mm thick Si-doped β-Ga₂O₃ single crystals by the EFG (Edge-defined Film-fed Growth) method. The growth direction and growth principal plane were set to [010] / (010), respectively, and the growth speed was 7~20 mm/h. The as-grown β-Ga₂O₃ single crystal was cut into various crystal planes (001, 100, ${\bar{2}}01$) and off-angles (1^o, 3^o, 4^o), and then surface processed. After processed, the homoepitaxial layer was grown on the epi-ready substrate using the HVPE (Halide vapor phase epitaxy) method. The processed samples and the epi-layer grown samples were analyzed by XRD, AFM, OM, and Etching to compare the surface properties according to the crystal plane and off-angle.