• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2006.05a
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• pp.194-197
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• 2006

Lead-free bismuth-layered perovskite ferroelectric europium-substituted $Bi_{4}Ti_{3}O_{12}(BTO)$ thin films have been successfully deposited on Pt/Ti/$SiO_2$/Si substrate by a sol-gel spin-coating process. $Bi(TMHD)_3,\;Eu(THMD)_3,\;Ti(OiPr)_4$ were used as the precursors, which were dissolved in 2-methoxyethanol. The thin films were annealed at various temperatures from $600^{\circ}\;to\;720^{\circ}C$ in oxygen ambient for 1 hr, which was followed by post-annealed for 1 hr after depositing a Pt electrode to enhance the electrical properties. X-ray diffraction (XRD) and scanning electron microscopy (SEM) were used to analyze the crystallinity and surface morphology of layered perovskite phase, respectively. The remanent polarization value of the BET thin films annealed at $720^{\circ}C\;was\;25.95{\mu}C/cm^2$ at an applied voltage of 5 V.

• Journal of Korean Vacuum Science & Technology
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• v.4 no.3
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• pp.73-77
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• 2000

Single crystal and polycrystalline Si thin films were doped with phosphorus by a 2-zone diffusion method to develop the low-resistivity polycrystalline Si electrode for a hemispherical grain. Solid phosphorus source was used in order to achieve uniformly and highly doped surface region of polycrystalline Si films having rough surface morphology. In case of 2-zone diffusion method, it is proved that the heavy doping near the surface area can be achieved even at a relatively low temperature. SIMS analysis revealed that phosphorus doping concentration in case of using solid P as a doping source was about 50 times as that of phosphine source at 750$^{\circ}C$. Also, ASR analysis revealed that the carrier concentration was about 50 times as that of phosphine. In order to evaluate the electrical characteristics of doped polycrystalline Si films for semiconductor devices, MOS capacitors were fabricated to measure capacitance of polycrystalline Si films. In ${\pm}$2 V measuring condition, Si films, doped with solid source, have 8% higher $C_{min}$ than that of unadditional doped Si films and 3% higher $C_{min}$ than that of Si films doped with $PH_3$ source. The leakage current of these films was a few fA/${\mu}m^2$. As a result, a 2-zone diffusion method is suggested as an effective method to achieve highly doped polycrystalline Si films even at low temperature.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.11
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• pp.4468-4472
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• 2010

SiOC films made by the inductively coupled plasma chemical vapor deposition were researched the relationship between the dielectric constant and the chemical shift. SiOC film obtained by plasma method had the main Si-O-C bond with the molecule vibration mode in the range of $930{\sim}1230\;cm^{-1}$ which consists of C-O and Si-O bonds related to the cross link formation according to the dissociation and recombination. The C-O bond originated from the elongation effect by the neighboring highly electron negative oxygen atoms at terminal C-H bond in Si-$CH_3$ of $1270cm^{-1}$. However, the Si-O bond was formed from the second ionic sites recombined after the dissociation of Si-$CH_3$ of $1270cm^{-1}$. The increase of the Si-O bond induced the redshift as the shift of peak in FTIR spectra because of the increase of right shoulder in main bond. These results mean that SiOC films become more stable and stronger than SiOC film with dominant C-O bond. So it was researched that the roughness was also decreased due to the high degree of amorphous structure at SiOC film with the redshift after annealing.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.854-859
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• 2016

Recently, GeSn is drawing great deal of interests as one of the candidates for group-IV-driven optical interconnect for integration with the Si complementary metal-oxide-semiconductor (CMOS) owing to its pseudo-direct band structure and high electron and hole mobilities. However, the large lattice mismatch between GeSn and Si as well as the Sn segregation have been considered to be issues in preparing GeSn on Si. In this work, we deposit the GeSn films on Si by DC magnetron sputtering at a low temperature of $250^{\circ}C$ and characterize the thin films. To reduce the stresses by GeSn onto Si, Ge buffer deposited under different processing conditions were inserted between Si and GeSn. As the result, polycrystalline GeSn domains with Sn atomic fraction of 6.51% on Si were successfully obtained and it has been demonstrated that the Ge buffer layer deposited at a higher sputtering power can relax the stress induced by the large lattice mismatch between Si substrate and GeSn thin films.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.10
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• pp.464-468
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• 2003

The double layers of $SiO_2$/$Si_3$$N_4$ have superior charge storage stability than a single layer of $SiO_2$. Many researchers are very interested in the charge storage mechanism of $SiO_2$/$Si_3$$N_4$ [1,2]. In this paper, the electrical characteristics of thermal oxide and atmospheric pressure chemical vapor deposition (APCVD) of $Si_4$$N_4$ have been investigated and explained using high frequency capacitance-voltage measurements. Additionally, this paper will describe capacitance-voltage characteristics for double layers of $SiO_2$/$Si_4$$N_4$ by "Athena", a semiconductor device simulation tool created by Silvaco, Inc.vaco, Inc.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.15 no.2
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• pp.57-60
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• 2005

Semiconductor carbon nanotube was grown on oxided silicon wafer with atmosphere pressure chemical vapor deposition (APCVD) method and investigated the electrical property after thermal oxidation at $300^{\circ}C$ in air. The electrical property was measured at room temperature in air after thermal oxidation at $300^{\circ}C$ for various times in air. Semiconductor carbon nanotube was steadily changed to metallic carbon nanotube as increasing of thermal oxidation times at $300^{\circ}C$ in air. Some removed area of carbon nanotube surface was shown with transmission electron microscopy (TEM) after thermal oxidation for 6 hours at $300^{\circ}C$ in air.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2004.05a
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• pp.97-100
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• 2004

We report $EU^{2+}$ activated green phosphor $Ba_{2}CaMgSi_{2}O_{8}:Eu^{2+}$. The phosphor absorbs ultroviolet radation and emits a green visible light. The phosphors were synthesized by conventional solid state reaction method. The high purity $BaCO_3$, $CaCO_3$, MgO, $SiO_2$, $Eu_{2}O_{3}$ were used as raw materials. The raw materials were mixed thoroughly with an appropriate amount of ethanol in an agate mortar and then dried at $90^{\circ}C$ for 2 hours. The mixture was sintered at $900^{\circ}C$ for 2 hours and reheated at the mild reducing atmosphere 5% $H_2$ gas mixed with 95% $N_2$ gas at about $900^{\circ}C$ to $1200^{\circ}C$ for 2 hours. The photoluminescence spectra of the phosphor powders were measured by a fluorescent spectrophotometer. The crystal structure of phosphor powders were investigated by X -ray diffractometer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.539-542
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• 2001

In SiC semiconductor device processing, it needs high temperature anneal for activation of ion implanted dopants. The macrosteps, 7~8nm in height, are formed on the surface of SiC substrates during activation anneal. We have investigated the effect of thermally-grown SiO$_2$layer on the suppression of macrostep formation during high temperature anneal. The cap oxide layer was found to be efficient for suppression of macrostep formation even though the annealing temperature is as high as the melting point of SiO$_2$. The thin cap oxide layer (10nm) was evaporated during anneal then the macrosteps were formed on SiC substrate. On the other hand the thicker cap oxide layer (50nm) remains until the anneal process ends. In that case, the surface was smoother and the macrosteps were rarely formed. The thermally-grown oxide layer is found to be a good material for the suppression of macrostep formation because of its feasibility of growing and processing. Moreover, we can choose a proper oxide thickness considering the evaporate rate of SiO$_2$at the given temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.65-65
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• 2009

High temperature silicon carbide Schottky diode was fabricated with Au deposited on poly 3C-SiC thin film grown on p-type Si(100) using atmospheric pressure chemical vapor deposition. The charge transport mechanism of the diode was studied in the temperature range of 300 K to 550 K. The forward and reverse bias currents of the diode increase strongly with temperature and diode shows a non-ideal behavior due to the series resistance and the interface states associated with 3C-SiC. The charge transport mechanism is a temperature activated process, in which, the electrons passes over of the low barriers and in turn, diode has a large ideality factor. The charge transport mechanism of the diode was analyzed by a Gaussian distribution of the Schottky barrier heights due to the Schottky barrier inhomogeneities at the metal-semiconductor interface and the mean barrier height and zero-bias standard deviation values for the diode was found to be 1.82 eV and $s_0$=0.233 V, respectively. The interface state density of the diode was determined using conductance-frequency and it was of order of $9.18{\times}10^{10}eV^{-1}cm^{-2}$.

• Journal of Information Display
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• v.13 no.2
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• pp.61-66
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• 2012

The double-layered Ti/Si barrier metal is demonstrated for the source/drain Cu interconnections in oxide semiconductor thin-film transistors (TFTs). The transmission electromicroscopy and ion mass spectroscopy analyses revealed that the double-layered barrier structure suppresses the interfacial reaction and the interdiffusion at the interface after thermal annealing at $350^{\circ}C$. The underlying Si layer was found to be very useful for the etch stopper during wet etching for the Cu/Ti layers. The oxide TFTs with a double-layered Ti/Si barrier metal possess excellent TFT characteristics. It is concluded that the present barrier structure facilitates the back-channel-etch-type TFT process in the mass production line, where the four- or five-mask process is used.