• Title/Summary/Keyword: SiC Semiconductor

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Realistic Simulations on Reverse Junction Characteristics of SiC and GaN Power Semiconductor Devices

  • Wei, Guannan;Liang, Yung C.;Samudra, Ganesh S.
    • Journal of Power Electronics
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    • v.12 no.1
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    • pp.19-23
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    • 2012
  • This paper presents a practical methodology for realistic simulation on reverse characteristics of Wide Bandgap (WBG) SiC and GaN p-n junctions. The adjustment on certain physic-based model parameters, such as the trap density and photo-generation for SiC junction, and impact ionization coefficients and critical field for GaN junction are described. The adjusted parameters were used in Synopsys Medici simulation to obtain a realistic p-n junction avalanche breakdown voltage. The simulation results were verified through benchmarking against independent data reported by others.

Investigation of the influence of substrate surface on the ZnO nanostructures growth (기판 표면의 영향에 의한 ZnO 나노 구조 성장에 관한 연구)

  • Ha, Seon-Yeo;Jung, Mi-Na;Park, Seung-Hwan;Yang, Min;Kim, Hong-Seung;Lee, Uk-Hyeon;Yao, Takafumi;Jang, Ji-Ho
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • v.9 no.1
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    • pp.1022-1025
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    • 2005
  • The effect of substrate surface to the formation of ZnO nanostructures has been investigated using Si (111), $Al_2O_3$(C-plane) $Al_2O_3$(A-plane), and $Al_2O_3$(R-plane) substrates. The growth temperature was controlled from 500$^{\circ}C$ ${\sim}$ 600$^{\circ}C$, and the luminescence properties were investigated by a series of photoluminescence (PL) measurements at the elevating temperatures. ZnO nanostructures grown on Si substrate show strong UV emission intensity along with green emission positioned at 3.22 eV and 2.5 eV, respectively. However, green emission was not observed from the ZnO nanostructures grown on $Al_2O_3$ substrates. It is explained in terms of the difference of the surface energy between Si and $Al_2O_3$. Also, the origin of UV emissions has been discussed by using the temperature-dependent PL. The distinction of the PL spectra is interpreted in terms of the difference of the impurity included in the nanostructures.

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Scanning Kelvin Probe Microscope analysis of Nano-scale Patterning formed by Atomic Force Microscopy in Silicon Carbide (원자힘현미경을 이용한 탄화규소 미세 패터닝의 Scanning Kelvin Probe Microscopy 분석)

  • Jo, Yeong-Deuk;Bahng, Wook;Kim, Sang-Cheol;Kim, Nam-Kyun;Koo, Sang-Mo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.11a
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    • pp.32-32
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    • 2009
  • Silicon carbide (SiC) is a wide-bandgap semiconductor that has materials properties necessary for the high-power, high-frequency, high-temperature, and radiation-hard condition applications, where silicon devices cannot perform. SiC is also the only compound semiconductor material. on which a silicon oxide layer can be thermally grown, and therefore may fabrication processes used in Si-based technology can be adapted to SiC. So far, atomic force microscopy (AFM) has been extensively used to study the surface charges, dielectric constants and electrical potential distribution as well as topography in silicon-based device structures, whereas it has rarely been applied to SiC-based structures. In this work, we investigated that the local oxide growth on SiC under various conditions and demonstrated that an increased (up to ~100 nN) tip loading force (LF) on highly-doped SiC can lead a direct oxide growth (up to few tens of nm) on 4H-SiC. In addition, the surface potential and topography distributions of nano-scale patterned structures on SiC were measured at a nanometer-scale resolution using a scanning kelvin probe force microscopy (SKPM) with a non-contact mode AFM. The measured results were calibrated using a Pt-coated tip. It is assumed that the atomically resolved surface potential difference does not originate from the intrinsic work function of the materials but reflects the local electron density on the surface. It was found that the work function of the nano-scale patterned on SiC was higher than that of original SiC surface. The results confirm the concept of the work function and the barrier heights of oxide structures/SiC structures.

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Numerical Study on CVI Process for SiC-Matrix Composite Formation (SiC 복합체 제조를 위한 화학기상침착공정에 대한 수치해석 연구)

  • Bae, Sung Woo;Im, Dongwon;Im, Ik-Tae
    • Journal of the Semiconductor & Display Technology
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    • v.14 no.2
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    • pp.61-65
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    • 2015
  • SiC composite materials are usually used to very high temperature condition such as thermal protection system materials at space vehicles, combustion chambers or engine nozzles because they have high specific strength and good thermal properties at high temperature. One of the most widely used fabrication methods of SiC composites is the chemical vapor infiltration (CVI) process. During the process, chemical gases including Si are introduced into porous preform which is made by carbon fibers for infiltration. Since the processes take a very long time, it is important to reduce the process time in designing the reactors and processes. In this study, both the gas flow and heat transfer in the reactors during the processes are analyzed using a computational fluid dynamics method in order to design reactors and processes for uniform, high quality SiC composites. Effects of flow rate and heater temperature as process parameters to the infiltration process were examined.

Impact of Interface Charges on the Transient Characteristics of 4H-SiC DMOSFETs

  • Kang, Min-Seok;Bahng, Wook;Kim, Nam-Kyun;Ha, Jae-Geun;Koh, Jung-Hyuk;Koo, Sang-Mo
    • Journal of Electrical Engineering and Technology
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    • v.7 no.2
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    • pp.236-239
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    • 2012
  • In this paper, we study the transient characteristics of 4H-SiC DMOSFETs with different interface charges to improve the turn-on rising time. A physics-based two-dimensional mixed device and circuit simulator was used to understand the relationship between the switching characteristics and the physical device structures. As the $SiO_2$/SiC interface charge increases, the current density is reduced and the switching time is increased, which is due primarily to the lowered channel mobility. The result of the switching performance is shown as a function of the gate-to-source capacitance and the channel resistance. The results show that the switching performance of the 4H-SiC DMOSFET is sensitive to the channel resistance that is affected by the interface charge variations, which suggests that it is essential to reduce the interface charge densities in order to improve the switching speed in 4H-SiC DMOSFETs.

Thermal Stability of the Cu/Co-Nb Multilayer Silicide Structure (Cu와 Co-Nb 이중층 실리사이드 계면의 열적안정성)

  • Lee, Jong-Mu;Gwon, Yeong-Jae;Kim, Yeong-Uk;Lee, Su-Cheon
    • Korean Journal of Materials Research
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    • v.7 no.7
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    • pp.587-591
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    • 1997
  • RBS와 XRD를 이용하여 C o-Nb이중층 실리사이드와 구리 배선층간의 열적안정성에 관하여 조사하였다. Cu$_{3}$Si등의 구리 실리사이드는 열처리시 40$0^{\circ}C$정도에서 처음 형성되기 시작하였는데, 이 때 형성되는 구리 실리사이드는 기판의 상부에 존재하던 준안정한 CoSi의 분해시에 발생한 Si원자와의 반응에 의한 것이다. 한편, $600^{\circ}C$에서의 열처리 후에는 CoSi$_{2}$층을 확산.통과한 Cu원자와 기판 Si와의 반응에 의하여 CoSi$_{2}$/Si계면에도 구리 실리사이드가 성장하였는데, 이렇게 구리 실리사이드가 CoSi$_{2}$/Si 계면에 형성되는 것은 Cu원자의 확산속도가 여러 중간층에서 Si 원자의 확산속도 보다 더 빠르기 때문이다. 열처리 결과 최종적으로 얻어진 층구조는 CuNbO$_{3}$/Cu$_{3}$Si/Co-Nb합금층/Nb$_{2}$O$_{5}$CoSi$_{2}$/Cu$_{3}$Si/Si이었다. 여기서 상부에 형성된 CuNbO$_{3}$는 Cu원자가 Nb$_{2}$O$_{5}$및 Co-Nb합금층과 반응하여 기지조직의 입계에 석출되어 형성된 것이다.

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A Study on the Reaction of Al-1% Si with Ti-silicide (Al-1% Si층과 Ti-silicide층의 반응에 관한 연구)

  • Hwang, Yoo-Sang;Paek, Su-Hyon;Song, Young-Sik;Cho, Hyun-Choon;Choi, Jin-Seog;Jung, Jae-Kyoung;Kim, Young-Nam;Sim, Tae-Un;Lee, Jong-Gil;Lee, Sang-In
    • Korean Journal of Materials Research
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    • v.2 no.6
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    • pp.408-416
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    • 1992
  • Stable TiS$i_2$was formed by RTA on single-Si and on poly-Si. Subsequently, an Al-1% Si layer with 600-nm thick was deposited on top of the TiS$i_2$, Finally, the specimens were annealed for 30min at 400-60$0^{\circ}C$in $N_2$ambient. The thermal stability of Al-1% Si/TiS$i_2$bilayer and interfacial reaction were investigated by measuring sheet resistance, Auger electron spectroscopy (AES), and scanning electron microscopy (SEM). The composition and phase of precipitates formed by the reaction of Al-1% Si with Ti-silicide were studied by energy dispersive spectroscopy (EDS), X-ray diffraction (XRD). In the case of single-Si substrate the reaction of Al-1% Si layer with TiS$i_2$layer resulted in precipitates, consuming all TiS$i_2$layer at 55$0^{\circ}C$. On the other hand, the disappearance of TiS$i_2$on poly-Si occurred at 50$0^{\circ}C$ and more precipitates were formed by the reaction of Al-1% Si/TiS$i_2$on potty-Si substrate than those of the reaction on single-Si substrate. This phenomenon resulted from the fact that Ti-silicide formed on poly-Si was more unstable than on single-Si by the effect of grain boundary. By EDS analysis the precipitates were found tobe composed of Ti, Al, and Si. X-ray diffraction showed the phase of precipitates to be theT$i_7$A$l_5$S$i_12$ternary compound.

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The Formation Technique of Thin Film Heaters for Heat Transfer Components (열교환 부품용 발열체 형성기술)

  • 조남인;김민철
    • Journal of the Semiconductor & Display Technology
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    • v.2 no.4
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    • pp.31-35
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    • 2003
  • We present a formation technique of thin film heater for heat transfer components. Thin film structures of Cr-Si have been prepared on top of alumina substrates by magnetron sputtering. More samples of Mo thin films were prepared on silicon oxide and silicon nitride substrates by electron beam evaporation technology. The electrical properties of the thin film structures were measured up to the temperature of $500^{\circ}C$. The thickness of the thin films was ranged to about 1 um, and a post annealing up to $900^{\circ}C$ was carried out to achieve more reliable film structures. In measurements of temperature coefficient of resistance (TCR), chrome-rich films show the metallic properties; whereas silicon-rich films do the semiconductor properties. Optimal composition between Cr and Si was obtained as 1 : 2, and there is 20% change or less of surface resistance from room temperature to $500^{\circ}C$. Scanning electron microscopy (SEM) and Auger electron spectroscopy (AES) were used for the material analysis of the thin films.

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Fabrication of Silica Nanoparticles by Recycling EMC Waste from Semiconductor Molding Process and Its Application to CMP Slurry (반도체 몰딩 공정에서 발생하는 EMC 폐기물의 재활용을 통한 실리카 나노입자의 제조 및 반도체용 CMP 슬러리로의 응용)

  • Ha-Yeong Kim;Yeon-Ryong Chu;Gyu-Sik Park;Jisu Lim;Chang-Min Yoon
    • Journal of the Korea Organic Resources Recycling Association
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    • v.32 no.1
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    • pp.21-29
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    • 2024
  • In this study, EMC(Epoxy molding compound) waste from the semiconductor molding process is recycled and synthesized into silica nanoparticles, which are then applied as abrasive materials contains CMP(Chemical mechanical polishing) slurry. Specifically, silanol precursor is extracted from EMC waste according to the ultra-sonication method, which provides heat and energy, using ammonia solution as an etchant. By employing as-extracted silanol via a facile sol-gel process, uniform silica nanoparticles(e-SiO2, experimentally synthesized SiO2) with a size of ca. 100nm are successfully synthesized. Through physical and chemical analysis, it was confirmed that e-SiO2 has similar properties compared to commercially available SiO2(c-SiO2, commercially SiO2). For practical CMP applications, CMP slurry is prepared using e-SiO2 as an abrasive and tested by polishing a semiconductor chip. As a result, the scratches that are roughly on the surface of the chip are successfully removed and turned into a smooth surface. Hence, the results present a recycling method of EMC waste into silica nanoparticles and the application to high-quality CMP slurry for the polishing process in semiconductor packaging.

Chemical structure evolution of low dielectric constant SiOCH films during plasma enhanced plasma chemical vapor deposition and post-annealing procedures

  • Xu, Jun;Choi, Chi-Kyu
    • Proceedings of the Korean Society Of Semiconductor Equipment Technology
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    • 2002.11a
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    • pp.34-46
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    • 2002
  • Si-O-C-H films with a low dielectric constant were deposited on a p-type Si(100) substrate using a mixture gases of the bis-trimethylsilyl-methane (BTMSM) and oxygen by an inductively coupled plasma chemical vapor deposition (ICPCYD). High density plasma of about $~10^{12}\textrm{cm}^{-3}$ is obtained at low pressure (<400 mTorr) with rf power of about 300W in ICPCVD where the BTMSM and $O_2$ gases are fully dissociated. Fourier transform infrared (FTIR) spectra and X-ray photoelectron spectroscopy (XPS) spectra show that the film has $Si-CH_3$ and OH-related bonds. The void within films is formed due to $Si-CH_3$ and OH-related bonds after annealing at $500^{\circ}C$ for the as-deposition samples. The lowest relative dielectric constant of annealed film at $500^{\circ}C$ is about 2.1.

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