• Korean Journal of Materials Research
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• v.1 no.3
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• pp.125-131
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• 1991

Boron penetration phenomenon of $p^{+}$ silicon gate with as-deposited amorphous or polycrystalline Si upon high temperature annealing was investigated using high frequency C-V (Capacitance-Volt-age) analysis, CCST(Constant Current Stress Test), TEM(Transmission Electron Microscopy) and SIMS(Secondary Ion Mass Spectroscopy), C-V analysis showed that an as-deposited amorphous Si gate resulted in smaller positive shifts in flatband voltage compared wish a polycrystalline Si gate, thus giving 60-80 percent higher charge-to-breakdown of gate oxides. The reduced boron penetration of amorphous Si gate may be attributed to the fewer grain boundaries available for boron diffusion into the gate oxide and the shallower projected range of $BF_2$ implantation. The relation between electron trapping rate and flatband voltage shift was also discussed.

• Journal of the Korean Vacuum Society
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• v.10 no.1
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• pp.44-50
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• 2001

Metal oxide semiconductor (MOS) structures containing nanocrystals are fabricated by using rapid thermal oxidations of amorphous silicon films. The amorphous films are deposited either by electron beam deposition method or by electron beam deposition assisted by Ar ion beam during deposition. Post oxidation of e-beam deposited film results in relatively small hysteresis of capacitance-voltage (C-V) and the flat band voltage shift, $\DeltaV_{FB}$ is less than 1V indicative of the formation of low density nanocrystals in $SiO_2$ near $SiO_2$/Si interface. By contrast, we observe very large hysteresis in C-V characteristics for oxidized ion-beam assisted e-beam deposited sample. The flat band voltage shift is larger than 22V and the hysteresis becomes even broader as increasing injection times of holes at accumulation condition and electrons at inversion condition. The result indicates the formation of slow traps in $SiO_2$ near $SiO_2$/Si interface which might be related to large density nanocrystals. Roughly estimated trap density is $1{\times}10^{13}cm^{-2}$. Such a large hysteresis may be explained in terms of the activation of adatom migration by Ar ion during deposition. The activated migration may increase nucleation rate of Si nuclei in amorphous Si matrix. During post oxidation process, nuclei grow into nanocrystals. Therefore, ion beam assistance during deposition may be very feasible for MOS structure containing nanocrystals with large density which is a basic building block for single electron memory device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04b
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• pp.45-46
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• 2009

We have fabricated advanced metal-oxide-semiconductor (MOS) capacitors with thin (${\approx}10\;nm$) Inductive-Coupled Plasma (ICP) CVD $Si_xN_y$ dielectric layers and investigated electrical properties of nitrided $SiO_2$/4H-SiC interface after oxidizing the $Si_xN_y$ in dry oxidation and/or $N_2$ annealing. An improvement of electrical properties have been revealed in capacitance-voltage (C-V) and current density-electrical field (J-E) measurements if compared with non-annealed oxidized-SiN. The improvements of SiC MOS capacitors formed by oxidized-SiN have been explained in this paper.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.101-102
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• 2005

SiC lateral power semiconductor device has high breakdown voltage and low on-state voltage drop due to the material characteristics. And, because the high breakdown voltage can be obtained, RESURF technique is mostly used in silicon power semiconductor devices. In this paper, we presents the electrical characteristics of the 4H-SiC RESURF LDMOSFET as a function of the epi-layer length, concentration and thickness. 240~780V of breakdown voltage can be obtained as a function of epi-layer length and thickness with same epi-layer concentration.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.32-35
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• 2000

Oxide-nitride-oxide(ONO) structures were formed by sequential radio frequency reactive magnetron sputtering method. The chemical composition and structure of these films were studied by using of secondary ion mass spectroscopy(SIMS) and Auger electron spectroscopy(AES) SIMS and AES experiments show the existence of nitridation at the SiO$_2$/Si substrate. The electrical characteristics of ONO films were evaluated by I-V and high frequency C-V measurements When the ONO films were annealed at 90$0^{\circ}C$ for 30 sec in $N_2$ ambient, the breakdown voltage increased and flat-band voltage decreased under high electric field.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.155-160
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• 2023

The potential performance benefits of Silicon Carbide(SiC) MOSFETs in high power, high frequency power switching applications have been well established over the past 20 years. In the past few years, SiC MOSFET offerings have been announced by suppliers as die, discrete, module and system level products. In high-voltage SiC vertical devices, major design concerns is the edge termination and cell pitch design Field Limiting Rings(FLR) based structures are commonly used in the edge termination approaches. This study presents a comprehensive analysis of the impact of variation of FLR and JFET region on the performance of a 3.3 kV SiC MOSFET during. The improvement in MOSFET reverse bias by optimizing the field ring design and its influence on the nominal operating performance is evaluated. And, manufacturability of the optimization of the JFET region of the SiC MOSFET was also examined by investigating full-map electrical characteristics.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.3
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• pp.576-583
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• 2018

Silicon carbide is considered to be a potentially useful material for high-temperature electronic devices, as its band gap is larger than that of silicon and the p-type and/or n-type conduction can be controlled by impurity doping. Particularly, porous n-type SiC ceramics fabricated from ${\beta}-SiC$ powder have been found to show a high thermoelectric conversion efficiency in the temperature region of $800^{\circ}C$ to $1000^{\circ}C$. For the application of SiC thermoelectric semiconductors, their figure of merit is an essential parameter, and high temperature (above $800^{\circ}C$) electrodes constitute an essential element. Generally, ceramics are not wetted by most conventional braze metals,. but alloying them with reactive additives can change their interfacial chemistries and promote both wetting and bonding. If a liquid is to wet a solid surface, the energy of the liquid-solid interface must be less than that of the solid, in which case there will be a driving force for the liquid to spread over the solid surface and to enter the capillary gaps. Consequently, using Ag with a relatively low melting point, the junction of the porous SiC semiconductor-Ag and/or its alloy-SiC and/or alumina substrate was studied. Ag-20Ti-20Cu filler metal showed promise as the high temperature electrode for SiC semiconductors.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.4
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• pp.373-377
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• 2004

We have investigated the electrical characterization of metal-oxide-semiconductor (MOS) capacitors formed on the inductively coupled plasma (ICP) etch-damaged both n- and p-type 4H-SiC. We found that there was an effect of a sacrificial oxidation treatment on the etch-damaged surfaces. Current-voltage and capacitance-voltage measurements of these MOS capacitors were used and referenced to those of prepared control samples without etch damage. It has been found that a sacrificial oxidation treatment can improve the electrical characteristics of MOS capacitors on etch-damaged 4H-SiC since the effective interface density and fixed oxide charges of etch-damaged samples have been found to increase while the breakdown field strength of the oxide decreased and the barrier height at the SiC-SiO$_2$ interface decreased for MOS capacitors on etch-damaged surfaces.

• Journal of Power Electronics
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• v.11 no.3
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• pp.381-388
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• 2011

This article presents the development of a model for SiC power diodes based on the physics of the semiconductor. The model is able to simulate the behavior of the dynamics of the charges in the N- region based on the stored charge inside the SiC power diode, depending on the working regime of the device (turn-on, on-state, and turn-off). The optimal individual calculation of the ambipolar diffusion length for every phase of commutation allows for solving the ambipolar diffusion equation (ADE) using a very simple approach. By means of this methodology development a set of differential equations that models the main physical phenomena associated with the semiconductor power device are obtained. The model is developed in Pspice with acceptable simulation times and without convergence problems during its implementation.

• KIEE International Transactions on Electrophysics and Applications
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• v.11C no.4
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• pp.99-106
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• 2001

An overview of Silicon Carbide (SiC) Static Induction Transistor (SIT) development is presented. Basic conduction mechanisms are introduced and discussed, including ohmic, exponential, and space charge limited conduction (SCLC) mechanisms. Additionally, the impact of velocity saturation and temperature effects on SCLC are reviewed. The small-signal model, breakdown voltage, power density, and different gate structures are also discussed, before a final review of published SiC SIT results. Published S-band (3-4 GHz) results include 9.5 dB of gain and output power of 120 W, and L-band (1.3 GHz) results include 400 W output power, 7.7 dB of gain, and power density of 16.7 W/cm.