• 한국재료학회지
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• 제14권5호
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• pp.343-347
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• 2004

We investigated the growth feasibility of polycrystalline Si film on mica substrate for the transfer of the layer to a plastic substrate. The annealing temperature was limited up to $600^{\circ}C$ because of crack development in the mica substrate. Amorphous Si film was deposited on mica substrate by PECVD and was crystallized by furnace annealing. During the annealing, bubbles were formed at the Si/mica interface. The bubble formation was avoided by the Ar-plasma treatment before amorphous Si deposition. A uniform and clean polycrystalline Si film was obtained by coating $NiCl_2$ on the amorphous Si film and annealing at $500^{\circ}C$ for 10 h. The conventional Si lithography was possible on the mica substrate and the devices fabricated on the substrate could be transferred to a plastic substrate.

• 한국세라믹학회지
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• 제36권6호
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• pp.604-610
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• 1999

Silicide layer structures and morphology degradation of the surface and interface of the silicide layers for he Co/refractory metal bilayer sputter-deposited on the P-doped polycrystalline Si substrate and subjected to rapid thermal annealing were investigated and compared with those on the single Si substrate. The CoSi-CoSi2 phase transition temperature is lower an morphology degradation of the silcide layer occurs more severely for the Co/refractorymetal bilayer on the P-doped polycrystalline Si substrate than on the single Si substrate. Also the final layer structure and the morphology of the films after silicidation annealing was found to depend strongly upon the interlayer metal. The layer structure after silicidation annealing of Co/Hf/doped-poly Si is Co-Hf alloy/polycrystalline CoSi2/poly Si substrate while that of Co/Nb is polycrystalline CoSi2/NbSi2/polycrystalline CoSi2/poly Si.

• 한국산학기술학회논문지
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• 제14권12호
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• pp.6106-6113
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• 2013

가솔린 엔진 차량용 삼원촉매담체는 주로 코제라이트 세라믹으로 제작되는 다공성 부품으로 엔진의 혼합기가 농후한 경우 삼원촉매의 열적 내구성이 급격히 떨어져 설계 내구 수명을 제대로 만족시키지 못하고 있다. 따라서 본 연구에서는 SiC 세라믹 촉매 담체의 내구성 평가에 사용할 기계적 물성치를 유한요소해석으로 구하기 위하여 등가물성평가방법을 이용하여 SiC 세라믹 하니컴 담체의 기계적 물성치를 유한요소해석용 시험편으로 구하였다. MOR과 탄성계수는 코제라이트 세라믹 하니컴 담체에 비하여 SiC 세라믹 하니컴 담체가 최소 2배와 9.3배 정도 크게 평가되고 있어 SiC 세라믹 하니컴 담체는 코제라이트 세라믹 하니컴 담체에 비하여 높은 구조 강도를 가지고 있다.

• 한국재료학회지
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• 제8권7호
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• pp.579-583
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• 1998

P가 고농도로 도핑된 다결정 Si 기판 위에 Co/Ti 이중층막을 스퍼터 증착하고 급속열처리함으로써 얻어지는 실리사이드 층구조, 실리사이드막의 응집, 그리고 도펀트의 재분포 등을 단결정 Si 기판 위에서의 그것들과 비교하여 조사하였다. 다결정 Si 기판위에 형성한 Co/Si 이중층을 열처리할 때 단결정 기판에서의 경우보다 $CoSi_2$로의 상천이는 약간 더 낮은 온도에서 시작되며, 막의 응집은 더 심하게 일어난다. 또한, 다결정 Si 기판내의 도펀트보다 웨이퍼 표면을 통하여 바깥으로 outdiffusion 함으로써 소실되는 양이 훨씬 더 많다. 이러한 차이는 다결정 Si 내에서의 결정립계 확산과 고농도의 도펀트에 기인한다. Co/Ti/doped-polycrystalline si의 실리사이드화 열처리후의 층구조는 polycrystalline CoSi2/polycrystalline Si 으로서 Co/Ti(100)Si을 열처리한 경우의 층구조인 Co-Ti-Si/epi-CoSi2/(100)Si 과는 달리 Co-Ti-Si층이 사라진다.

• 대한전자공학회논문지
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• 제26권11호
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• pp.1672-1678
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• 1989

Major problems preventing the device-quality GaAs/Si heterostructure are the lattice mismatch of about 4% and difference in thermal expansion coefficient by a factor of 2.64 between Si and GaAs. Ge is a good candidate for the buffer layer because its lattice parameter and thermal expansion coefficient are almost the same as those of GaAs. As a first step toward developing heterostructure such as GaAs/Ge/Si entirely by a home-built PAE (plasma-assisted epitaxy), Ge films have been deposited on p-type Si (100)substrate by the plasma assisted evaporation of solid Ge source. The characteristics of these Ge/Si heterostructure were determined by X-ray diffraction, SEM and Auge electron spectroscope. PAE system has been successfully applied to quality-good Ge layer on Si substrate at relatively low temperature. Furthermore, this system can remove the native oxide(SiO2) on Si substrate with in-situ cleaning procedure. Ge layer grown on Si substrate by PAE at substrate temperature of 450\ulcorner in hydrogen partial pressure of 10mTorr was expected with a good buffer layer for GaAs/Ge/Si heterostructure.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.155.2-155.2
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• 2013

Strain-relaxed SiGe layer on Si substrate has numerous potential applications for electronic and opto- electronic devices. SiGe layer must have a high degree of strain relaxation and a low dislocation density. Conventionally, strain-relaxed SiGe on Si has been manufactured using compositionally graded buffers, in which very thick SiGe buffers of several micrometers are grown on a Si substrate with Ge composition increasing from the Si substrate to the surface. In this study, a new plasma process, i.e., the combination of PIII&D and HiPIMS, was adopted to implant Ge ions into Si wafer for direct formation of SiGe layer on Si substrate. Due to the high peak power density applied the Ge sputtering target during HiPIMS operation, a large fraction of sputtered Ge atoms is ionized. If the negative high voltage pulse applied to the sample stage in PIII&D system is synchronized with the pulsed Ge plasma, the ion implantation of Ge ions can be successfully accomplished. The PIII&D system for Ge ion implantation on Si (100) substrate was equipped with 3'-magnetron sputtering guns with Ge and Si target, which were operated with a HiPIMS pulsed-DC power supply. The sample stage with Si substrate was pulse-biased using a separate hard-tube pulser. During the implantation operation, HiPIMS pulse and substrate's negative bias pulse were synchronized at the same frequency of 50 Hz. The pulse voltage applied to the Ge sputtering target was -1200 V and the pulse width was 80 usec. While operating the Ge sputtering gun in HiPIMS mode, a pulse bias of -50 kV was applied to the Si substrate. The pulse width was 50 usec with a 30 usec delay time with respect to the HiPIMS pulse. Ge ion implantation process was performed for 30 min. to achieve approximately 20 % of Ge concentration in Si substrate. Right after Ge ion implantation, ~50 nm thick Si capping layer was deposited to prevent oxidation during subsequent RTA process at $1000^{\circ}C$ in N2 environment. The Ge-implanted Si samples were analyzed using Auger electron spectroscopy, High-resolution X-ray diffractometer, Raman spectroscopy, and Transmission electron microscopy to investigate the depth distribution, the degree of strain relaxation, and the crystalline structure, respectively. The analysis results showed that a strain-relaxed SiGe layer of ~100 nm thickness could be effectively formed on Si substrate by direct Ge ion implantation using the newly-developed PIII&D process for non-gaseous elements.

• 한국전기전자재료학회논문지
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• 제11권4호
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• pp.267-273
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• 1998

The band structures of $Si_{1-x}Ge_x$ layers grown on $Si_{1-y}Ge_y$ substrate are calculated using k$\cdot$p and strain Hamiltonians. The hole drift mobilities in the plane direction are then calculated by taking into account the screening effect and the density-of-states of the impurity band. When $Si_{1-x}Ge_x$ is grown on Si substrate, the mobilities of (110) and (111) $Si_{1-x}Ge_x$ layers are larger than that of (001) $Si_{1-x}Ge_x$. However, due to the large defect and surface scattering, (110) and (111) $Si_{1-x}Ge_x$ layers may not be useful for the development of the fast device. Meanwhile, when Si is grown on $Si_{1-y}Ge_y$ substrate, the mobilities of (001) and (110) Si layers are greatly enhanced. Based on the amount of defect and the surface scattering, it is expected that Si grown on (001) $Si_{1-y}Ge_y$ substrate, where the Ge contents is larger than 10%(y>0.1), has the highest mobility.

• 한국결정학회지
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• 제12권3호
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• pp.166-170
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• 2001

실리콘 기판에 도핑되어 있는 도판트는 종류에 따라 코발트와 실리콘 기판과의 반응에 영향을 준다. 인은 붕소나 비소에 비해 코발트와 실리콘과의 반응을 억제하여 저온 열처리 동안에 CoSi₂대신에 CoSi가 형성되도록 한다. CoSi층 내에서의 확산원소는 Si으로, CoSi 층은 Co/CoSi 계면에서 성장하며 반응에 참여하는Si 소모에 의해 생기는 기판의 빈 공간을 태우기 위해 Si 기판쪽으로 이동한다. 게이트 측벽에서는 접촉되어 있는 게이트 산화막과의 결합에 의해 CoSi층의 이동이 억제된다. 따라서 기판의 빈 공간을 태우지 못하게 되어 게이트 측벽 아래에 기공이 형성된다.

• ETRI Journal
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• 제26권3호
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• pp.281-284
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• 2004

We demonstrate a new fabrication method for adjusting the temperature dependence of a polymeric arrayed-waveguide grating (AWG) on a Si substrate. A temperature-dependent wavelength shift of-0.1nm/$^{\circ}C$ in a polymeric AWG on a Si substrate is reduced of+0.1nm/$^{\circ}C$ by detaching part of the polymer film, including the grating channel region of the AWG, from the Si substrate while the other parts remain fixed on the substrate.

• 한국재료학회지
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• 제17권2호
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• pp.115-120
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• 2007

Polycrystalline silicon (poly-Si) thin film transistors (TFTs) might be fabricated on the mica substrate and transferred to a flexible plastic substrate because mica can be easily cleaved into a thin layer. To overcome the adhesion and stress problem between poly-Si film and mica substrate, a buffer layer consisting of $SiO_x/Ta/Ti$ three layers has been developed. The $SiO_x$ layer is for electrical isolation, the Ti layer is for adhesion of $SiO_{x}$ and mica. and Ta is for stress relief between $SiO_x$ and Ti. A TFT was fabricated on the mica substrate by a conventional Si process and was successfully transferred to a plastic substrate.