• Transactions of the Society of Information Storage Systems
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• v.1 no.2
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• pp.182-187
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• 2005

A large area micro mirror is an optical element that functions as changing an optical path by reflection in integrated optical system. We fabricated the large area silicon mirror by anisotropic etching using MEMS for implementation of integrated optical pickup. In this work, we report the optimum conditions to better fabricate and design, greatly improve mirror surface quality. To obtain mirror surface of $45^{\circ},\;9.74^{\circ}$ off-axis silicon wafer from (100) plane was used in etching condition of $80^{\circ}C$ with 40wt.% KOH solution. After wet etching, polishing process by MR fluid was applied to mirror surface for reduction of roughness. In the next step, after polymer coating on the polished Si wafer, the Si mirror was fabricated by UV curing using a trapezoid bar-type way structure. Finally, we obtained peak to valley roughness about 50 nm in large area of $mm^2$ and it is applicable to optical pickup using blu-ray wavelength as well as infrared wavelength.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.419-420
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• 2009

The authors fabricated the nanostructural patterns on the surface of SiN antireflection layer of polycrystalline Si solar cell and the surface of crystalline Si wafer using anodic aluminum oxide (AAO) masks in an inductively coupled plasma(ICP) etching process. The AAO nanopattern mask has the hole size of about 70~80nm and an ave rage lattice constant of 100nm. The transferred nano-patterns were observed by the scanning electron microscope (SEM) and the enhancement of solar cell efficiency will be presented.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.47-51
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• 2000

A modified direct bonding technique employing a wet chemical deposition of $SiO_2$ film on a wafer surface to be bonded is proposed for the fabrication of Si-$SiO_2$-Si structures. Structural and electrical quality of the bonded wafers is studied. Satisfied insulating properties of interfacial $SiO_2$ layers are demonstrated. Elastic strain caused by surface morphology is investigated. The diminution of strain in the grooved structures is semi-quantitatively interpreted by a model considering the virtual defects distributed over the interfacial region.

• Journal of the Korean institute of surface engineering
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• v.24 no.4
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• pp.196-205
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• 1991

Multi-level thin films are very important in ULSI applications because of their high electromigration resistance. This study presents the effects of titanium, titanium nitride and titanium tungsten underlayers of the stability of multi-aluminum thin films during isothermal annealing. High purity Al(99.999%) films have been electron-beam evaporated on Ti, TiN, TiW films formed on SiO2/Si (P-type(100))-wafer substrates by RF-sputtering in Ar gas ambient. The hillock growth was increased with annealing temperatures. Growth of hillocks was observed during isothermal annealing of the thin films by scanning electron microscopy. The hillock growth was believed to appear due to the recrystallization process driven by stress relaxation during isothermal annealing. Thermomigration damage was also presented in thin films by grain boundary grooving processes. It is shown that underlayers of Al/TiN/SiO2, Al/TiW/SiO2 thin films are preferrable to Al/SiO2 thin film metallization.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1999.05a
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• pp.128-133
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• 1999

In recent years, LSI devices have become more powerful and lower-priced, caused by a development of various wafer materials and an increase in the diameter of wafers. On the other hand, these have created some serious problems in manufacturing of wafers because materials used as semiconductor substrate are very brittle. In view of this fact, there are some trials to apply shear-mode(or ductile-mode) grinding for efficient manufacturing of semiconductor wafers instead of conventional lapping process. In fact grinding process that has not only more excellent degree of accuracy but also more adaptable to fully automated manufacturing than lapping, is already used in Si machining field. This paper described the elementary studies to establish the grinding technology of wafers. First, we investigated the variation of grinding force and the transition of grinding mode as various grinding conditions. Then, it was inspected that the change of grinding force affected the integrity such as the topography and the roughness of ground surfaces, and led to the chemical defects generation and distribution in damaged layer. The degree of defects was estimated by FT-IR(Fourier Transformed Infrared) Spectroscopy and Auger Electron Spectroscopy

• ETRI Journal
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• v.25 no.2
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• pp.65-72
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• 2003

To achieve cost and size reductions, we developed a low cost manufacturing technology for RF substrates and a high performance passive process technology for RF integrated passive devices (IPDs). The fabricated substrate is a conventional 6" Si wafer with a 25${\mu}m$ thick $SiO_2$ surface. This substrate showed a very good insertion loss of 0.03 dB/mm at 4 GHz, including the conductive metal loss, with a 50 ${\Omega}$ coplanar transmission line (W=50${\mu}m$, G=20${\mu}m$). Using benzo cyclo butene (BCB) interlayers and a 10 ${\mu}m$ Cu plating process, we made high Q rectangular and circular spiral inductors on Si that had record maximum quality factors of more than 100. The fabricated inductor library showed a maximum quality factor range of 30-120, depending on geometrical parameters and inductance values of 0.35-35 nH. We also fabricated small RF IPDs on a thick oxide Si substrate for use in handheld phone applications, such as antenna switch modules or front end modules, and high-speed wireless LAN applications. The chip sizes of the wafer-level-packaged RF IPDs and wire-bondable RF IPDs were 1.0-1.5$mm^2$ and 0.8-1.0$mm^2$, respectively. They showed very good insertion loss and RF performances. These substrate and passive process technologies will be widely utilized in hand-held RF modules and systems requiring low cost solutions and strict volumetric efficiencies.

• Korean Journal of Materials Research
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• v.20 no.12
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• pp.645-648
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• 2010

The structure and morphology of epitaxial layer defects in epitaxial Si wafers produced by the Czochralski method were studied using focused ion beam (FIB) milling, scanning electron microscopy (SEM), and transmission electron microscopy (TEM). Epitaxial growth was carried out in a horizontal reactor at atmospheric pressure. The p-type Si wafers were loaded into the reactor at about $800^{\circ}C$ and heated to about $1150^{\circ}C$ in $H_2$. An epitaxial layer with a thickness of $4{\mu}m$ was grown at a temperature of 1080-$1100^{\circ}C$. Octahedral void defects, the inner walls of which were covered with a 2-4 nm-thick oxide, were surrounded mainly by $\{111\}$ planes. The formation of octahedral void defects was closely related to the agglomeration of vacancies during the growth process. Cross-sectional TEM observation suggests that the carbon impurities might possibly be related to the formation of oxide defects, considering that some kinds of carbon impurities remain on the Si surface during oxidation. In addition, carbon and oxygen impurities might play a crucial role in the formation of void defects during growth of the epitaxial layer.

• The Journal of the Acoustical Society of Korea
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• v.10 no.3
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• pp.19-30
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• 1991

The surface properties such as energy gap, exciton, shallow trap level, deep trap level, type inversion with annealing and metastable state of $EL_2$ level of SI GaAs wafers and the conductivity distribution of 2 inch Cr doped GaAs wafer were investigated using nondestructive TAV(transverse acoustoelectric voltage) technique. The TAV is generated when SAW and semiconductor interact. We also have tried newly SAW oscillator technique to investigate the surface properties of semiconductor wafers and we have shown the validity of this technique.

• Journal of the Korean institute of surface engineering
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• v.40 no.6
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• pp.279-282
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• 2007

Cr-Mo-Si-C-N coatings were deposited on steel and Si wafer by a hybrid system of AIP and sputtering techniques using Cr, Mo and Si target in $Ar/N_2/CH_4$ gaseous mixture. Instrumental analyses of XRD and XPS revealed that the Cr-Mo-Si-C-N coatings must be a composite consisting of fine(Cr, Mo and Si)(C and N) crystallites and amorphous $Si_3N_4$ and SiC. The hardness value of Cr-Mo-Si-C-N coatings significantly increased from 41 GPa of Cr-Mo-C-N coatings to about 53 GPa with Si content of 9.3 at.% due to the refinement of (Cr, Mo and Si)(C and N) crystallites and the composite microstructure characteristics. A systematic investigation of the microstructures and mechanical properties of Cr-Mo-Si-C-N coatings prepared with various Si contents is reported in this paper.

• Journal of the Korean institute of surface engineering
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• v.34 no.1
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• pp.33-38
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• 2001

10cm-diameter Si(100)∥$1.3\mu\textrm{m}$-X$1.3_2$X$1.3\mu\textrm{m}$-$SiO_2$∥Si(100) afers were prepared using a fast linear annealing (FLA) equipment. 1.3$\mu\textrm{m}$-thick $SiO_2$ films were grown by dry oxidation process. After cleaning and premating the wafers in a class 100 clean room, they were heat treated using with the FLA and conventional electric furnace. Bonded area and bond strength of wafer pairs were measured using a infrared (IR) camera and razor blade crack opening method, respectively. It was confinmed that the bonded area by FLA was around 99% and the bond strength value reached 2172mJ/$\m^2$, which is equivalent to theoritical bond strength. Our result implies that thick $SiO_2$ SOI may be prepared more easily by using $SiO_2$$SiO_2$ bonding interfaces then those of Si/$SiO_2$'s.