• Proceedings of the KIEE Conference
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• 2004.11a
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• pp.275-277
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• 2004

This paper presents design and fabrication of micromachined accelerometer using $100{\mu}m$ thick SiOG substrate. The proposed accelerometer has a resonant frequency, 6kHz. To reduce the off-axis sensitivity of the accelerometer, the mode characteristic of the accelerometer is investigated using ANSYs modal analysis. Because the accelerometer is fabricated using an SiOG substrate, it is expected to be integrated as one-chip IMU sensor with a gyroscope using an SiOG substrate.

• Korean Journal of Materials Research
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• v.14 no.2
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• pp.133-140
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• 2004

We carried out anodic aluminum oxide (AAO) on a Si and a sapphire substrate. For anodic oxidation of Al two types of specimens prepared were Al(0.5 $\mu\textrm{m}$)!Si and Al(0.5 $\mu\textrm{m}$)/Ti(0.1 $\mu\textrm{m}$)$SiO_2$(0.1 $\mu\textrm{m}$)/GaN(2 $\mu\textrm{m}$)/Sapphire. Surface morphology of Al film was analyzed depending on the deposition methods such as sputtering, thermal evaporation, and electron beam evaporation. Without conventional electron lithography, we obtained ordered nano-pattern of porous alumina by in- situ process. Electropolishing of Al layer was carried out to improve the surface morphology and evaluated. Two step anodizing was adopted for ordered regular array of AAO formation. The applied electric voltage was 40 V and oxalic acid was used as an electrolyte. The reference electrode was graphite. Through the optimization of process parameters such as electrolyte concentration, temperature, and process time, a regular array of AAO was formed on Si and sapphire substrate. In case of Si substrate the diameter of pore and distance between pores was 50 and 100 nm, respectively. In case of sapphire substrate, the diameter of pore and distance between pores was 40 and 80 nm, respectively

• Journal of the Korean Vacuum Society
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• v.7 no.1
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• pp.29-34
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• 1998

The solid-phase crystallization (SPC) of plasma-enhanced chemical vapor depsoited (PECVD) amorphous silicon (a-Si) films ha s been investigated by x-ray diffraction (XRD). The a-Si films were prepared on Si (100) wafers using $SiH_4$ gas and without $H_2$ dilution at the substrate temperatures between $120^{\circ}C$ and $380^{\circ}C$, and than annealed at $600^{\circ}C$ for crystallization. The annealed samples exhibited (111), (220), and (311) XRD peaks with preferential orientation of (111). The XRD peak intensities increased as the substrate temperature decreased, and the $H_2$dilution suppressed the solid-phase crystallization. The average grain size estimated by XRD analysis for the (111) texture has increased from about 10 nm to about 30 nm, as the substrate temperature decreased. The deposition rate also increased with the decreasing substrate temperature and the grain size was closely dependent on the deposition rate of the films. The grain size enhancement was attributed to an increase of the structural disorder of the Si network.

• Korean Journal of Materials Research
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• v.9 no.5
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• pp.491-495
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• 1999

In this study, we focus on Ca contaminant which affects on the roughness Si substrate after thermal process. The initial Si substrates were contaminated intentionally by using a standard Ca solution. The contamination levels of Ca impurity were measured by TXRF and the chemical composition of that was analyzed by AES. Then we gre the thermal oxide to investigate the effect of Ca contaminants. The microroughness of the Si surface, the thermal oxide surface, and the surface after removing the thermal oxide were measured to examine the electrical characteristics. The initial substrates that were contaminated with the standard solution of Ca exhibited the contamination levels of 10\ulcorner~10\ulcorneratoms/$\textrm{cm}^2$ which was measured by TXRF. The Ca contaminants were detected by AES and exhibited the peaks of Ca, SI, C and O.After intentional contamination, the surface microroughness of this initial substrate was increased from $1.5\AA$ to 4$\AA$ as contamination levels became higher. The microroughness of the thermal oxide surfaces of both contaminated and bare Si substrates exhibits similar values. But the microroughness of the contaminated$ Si/SiO_2$ interface was increased as contamination increased. The thermal oxide of contaminated substrate exhibited the small minority carrier diffusion length, low breakdown voltage, and slightly high leakage current.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.8
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• pp.505-509
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• 2016

We have investigated the characteristics of amorphous silicon (a-Si) thin-film solar cell by inserting barrier layer. The conversion efficiency of a-Si thin-film solar cells on graphite substrate shows nearly zero because of the surface roughness of the graphite substrate. To enhance the performance of solar cells, the surface morphology of the back side were modified by changing the barrier layer on graphite. The surface roughness of graphite substrate with the barrier layer grown by plasma enhanced chemical vapor deposition (PECVD) reduced from ~2 um to ~75 nm. In this study, the combination of the barrier layer on graphite substrate is important to increase solar cell efficiency. We achieved ~ 7.8% cell efficiency for an a-Si thin-film solar cell on graphite substrate with SiNx/SiOx stack barrier layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.116-117
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• 2006

I-D ZnO nanostructures were fabricated by thermal evaporation method on Si(100), GaN and $Al_2O_3$ substrates without a catalyst at the reaction temperature of $700^{\circ}C$. Only pure Zn powder was used as a source material and Ar was used as a carrier gas. The shape and growth direction of synthesized ZnO nanostructures is determined by the crystal structure and the lattice mismatch between ZnO and substrates. The ZnO nanostructure on Si substrate were inclined regardless of their substrate orientation. The origin of ZnO/Si interface is highly lattice-mismatched and the surface of the Si substrate inevitably has the $SiO_2$ layer. The ZnO nanostructure on the $Al_2O_3$ substrate was synthesized into the rod shape and grown into particular direction. For the GaN substrate, however, ZnO nanostructure with the honeycomb-like shape was vertically grown, owing to the similar lattice parameter with GaN substrate.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.611-611
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• 2013

In this study, iron oxide nanoclusters layer (Nc) was prepared onto functionalized silicon substrate by wet method. The amine-terminated SAM fabricated on silicon substrate (APTMS/Si) was carried out by UV-treatment and immersed into the FeCl3/HCl aqueous solution. Then, Nc were immobilized onto oxidized SAM silicon substrate (SAMs/Si) through electrostatic interaction between cationic Nc and anionic SAMs/Si. This catalytic layer (Nc/SAMs/Si) was used to grow carbon nanotubes (CNTs). The characterization results clearly show that the well-graphitized CNTs were synthesized by using functionalized silicon substrate as a template having appropriate density of catalyst. These consequences show that SAM containing template is important to achieve the effective layer of catalyst to synthesize CNTs.

• Journal of the Semiconductor & Display Technology
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• v.5 no.2 s.15
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• pp.33-36
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• 2006

Many issues arose to use the Pb-free solder as adhesive materials in MEMS ICs and packaging. Then this study for easy and simple sealing method using adhesive materials was carried out to maintain hermetic characteristic in MEMS Package. In this study, Hermetic characteristic using negative PR (XP SU-8 3050 NO-2) as adhesive at the interface of Si test coupon/glass substrate and Si test coupon/LTCC substrate was examined. For experiment, the dispenser pressure was 4 MPa and the $200\;{\mu}m{\Phi}$ syringe nozzle was used. 3.0 mm/sec as speed of dispensing and 0.13 mm as the gap between Si test coupon and nozzle was selected to machine condition. 1 min at $65^{\circ}C$ and 15 min at $95^{\circ}C$ as Soft bake, $200\;mj/cm^2$ expose in 365 nm wavelength as UV expose, 1 min at $65^{\circ}C$ and 6 min at $95^{\circ}C$ as Post expose bake, 60 min at $150^{\circ}C$ as hard bake were selected to activation condition of negative PR. Hermetic sealing was achieved at the Si test coupon/ glass substrate and Si test coupon/LTCC substrate. The leak rate of Si test coupon/glass substrate was $5.9{\times}10^{-8}mbar-l/sec$, and there was no effect by adhesive method. The leak rate of Si test coupon/LTCC substrate was $4.9{\times}10^{-8}mbar-l/sec$, and there was no effect by dispensing cycle. Better leak rate value could be achieved to use modified substrate which prevent PR flow, to increase UV expose energy and to use system that controls gap automatically with vision.

• Journal of the Korean Ceramic Society
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• v.36 no.1
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• pp.55-60
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• 1999

${\beta}$-SiC thin film was deposited on a Si substrate without buffer layer using a single precursor of Hexamethyldisilane (Si2(CH3)6) by chemical vapor deposition method. HCI gas was introduced into hexamethyldisilane /H2 gas mixture, and the feeding schedule of HCI and precursor gases was modified in order to enhance the selectivity of SiC deposition between a Si substrate and a SiO2 mask. The effect of HCI gas on the surface roughness of the SiC film was investigated and typical electrical properties of the SiC film were also investigated by Hall measurement.

• Journal of the Korean Vacuum Society
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• v.11 no.1
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• pp.50-58
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• 2002

The growth of GaN films on Si substrate has many advantages in that Si is less expensive than sapphire substrate and that integration of GaN-based devices with Si substrate is easier The difference of lattice constant and thermal expansion coefficient between GaN and Si is larger than those between GaN and sapphire. However, which results in many defects into the grown GaN. In order to obtain high duality GaN films on Si substrate, we need to reduce defects using the buffer layer such as AlN. In this study, we prepared three types of AlN buffer layer with various crystallinity on Si (111) substrate using MOCVD, Sputtering and MOMBE methods. GaN was grown by MOCVD on three types of AlN/Si substrate. Using TEM and XRD, we carried out comparative investigation of growth and properties of GaN deposited on the various AlN buffers by characterizing lattice coherency, crystallinity, growth orientation and defects formed (voids, stacking faults, dislocations, etc). It is found that the crystallinity of AlN buffer layer has strong effects on growth of GaN. The AlN buffer layers grown by MOCVD and MOMBE showed the reduction of out-of-plane misorientation of GaN at the initial growth stage.