• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.3-4
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• 2005

Germanium nanocrystals(NCs) were formed in the silicon dioxide($SiO_2$) on Si layers by Ge implantation and rapid thermal annealing process. The density and mean size of Ge-NCs heated at $800^{\circ}C$ during 10 min were confirmed by High Resolution Transmission Electron Microscopy. Capacitance versus voltage(C-V) measurements of MOS capacitors with single $Al_2O_3$ capping layers were performed in order to study electrical properties. The C-V results exhibit large threshold voltage shift originated by charging effect in Ge-NCs, revealing the possibility that the structure is applicable to Nano Floating Gate Memory(NFGM) devices.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.4-4
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• 2004

• 한국광물학회지
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• 제21권1호
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• pp.27-35
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• 2008

천연 광물소재를 양이온 치환하여 환경개선재로 응용되고 있는 $Lumilite^{(R)}$의 원료 중 원광의 광물학적 특징을 분석하고 구성광물의 나노결정의 발달특징을 관찰하였다. 이를 위하여 편광현미경에 의한 조직관찰, XRD, SEM, FTIR, XRF 분석을 실시하였다. 구성 광물상은 클리높틸로라이트, 일라이트, 석영, 알바이트 사장석이며, 본 시료는 미립질의 치밀한 조직을 가지는 것이 특징이다. 나노결정의 크기는 $70{\sim}100\;nm$ 범위가 흔하면, 비교적 등립질 내지 반등립질로 구성된다. 나노결정들의 단면은 아원형 내지 완만한 각형이며, 나노결정의 표면에는 수 nm 크기의 원형돌기가 거의 균질하게 분포한다. 전시료의 화학조성은 $SiO_2$ $74.22{\sim}75.65\;wt.%$, $Al_2O_3$ $13.25{\sim}13.72\;wt.$, CaO $4.23{\sim}5.15\;wt.%$이며, 그 외 주성분과 수분은 미량으로 함유된다. 원료물질은 결정학적으로 $500^{\circ}C$까지는 안정한 상을 유지하나, $700^{\circ}C$에서는 구조가 거의 파괴된다. $Lumilite^{(R)}$가 흡착능력이 뛰어나고 높은 양이온치환능력을 가지는 것은 나노결정들이 잘 발달하고, 이들 사이에는 다양한 미세공극이 잘 발달하기 때문인 것으로 보인다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권2호
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• pp.68-73
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• 2006

We propose a damascene gate FinFET with Si nanocrystals implemented on bulk silicon wafer for low voltage flash memory device. The use of optimized SRON (Silicon-Rich Oxynitride) process allows a high degree of control of the Si excess in the oxide. The FinFET with Si nanocrystals shows high program/erase (P/E) speed, large $V_{TH}$ shifts over 2.5V at 12V/$10{\mu}s$ for program and -12V/1ms for erase, good retention time, and acceptable endurance characteristics. Si nanocrystal memory with damascene gate FinFET is a solution of gate stack and voltage scaling for future generations of flash memory device. Index Terms-FinFET, Si-nanocrystal, SRON(Si-Rich Oxynitride), flash memory device.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 제5회 영호남 학술대회 논문집
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• pp.93-93
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• 2003

Photoluminescence(PL) properties of Silicon nanocrystals (nc-Si) as a function of temperature is reported to consider the mechanism of PL. Nc-Si has been made by $Si^+$ ion-implantation into thermal $SiO_2$ and subsequent annealing. And after gold had been diffused at the same samples above, the resultant PL spectra has been compared to the PL spectra from the non-gold doped nc-Si. PL peak energy variation from nc-Si is same with the variation of energy bandgap of bulk silicon as temperature changes from 6 K to room temperature. This result may mean nc-Si is still indirect transition material like bulk silicon. Gold doped nc-Si reveals short peak wavelength of PL spectrum than gold undoped one. PL peak shift through gold doing process shows clearly the PL mechanism is not from defect or interface states. PL intensity increases from 6K to a certain temperature and then decrease to room temperature. This characteristic with temperature shows that phonon have a role for the luminescence as theory explains that electron and hole can be recombined radiatively by phonon's assist in nc-Si, which is almost impossible in bulk silicon. Therefore luminescence is observed in nc-Si constructed less than a few of unit cell and the peak energy of luminescence can be higher than the bulk bandgap energy by the bandgap widening effect occurs in nanostructure.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제37회 하계학술대회 초록집
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• pp.78-78
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• 2009

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1341-1342
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• 2006

Electrical characteristics of field-effect thin film transistors (TFTs) with p-channels of CdTe/CdHgTe core-shell nanocrystals are investigated in this paper. For the fabrication of bottom- and top-gate TFTs, CdTe/CrHgTe nanocrystals synthesized by colloidal method are first dispersed on oxidized p+ Si substrates by spin-coating, the dispersed nanoparticles are sintered at $150^{\circ}C$ to form the channels for the TFTs, and $Al_{2}O_{3}$ layers are deposited on the channels. A representative bottom-gate field-effect TFT with a bottom-gate $SiO_2$ layer exhibits a mobility of $0.21cm^2$/ Vs and an Ion/Ioff ratio of $1.5{\times}10^2$ and a representative top-gate field-effect TFT with a top-gate $Al_{2}O_{3}$ layer provides a field-effect mobility of $0.026cm^2$/ Vs and an Ion/Ioff ratio of $2.5{\times}10^2$. $Al_{2}O_{3}$ was deposited for passivation of CdTe/CdHgTe core-shell nanocrystal layer, resulting in enhanced hole mobility, Ior/Ioff ratio by 0.25, $3{\times}10^3$, respectively. The CdTe/CdHgTe nanocrystal-based TFTs with bottom- and top gate geometries are compared in this paper.

• 한국광학회:학술대회논문집
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• 한국광학회 2009년도 창립 20주년기념 특별학술발표회
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• pp.353-354
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• 2009

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제37회 하계학술대회 초록집
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• pp.222-222
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• 2009