• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.281-284
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• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1261-1268
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• 2013

This study proposes a voltage and reactive coordinative control strategy with distributed generator (DG) in a distribution power system. The aim is to determine the optimum dispatch schedules for an on-load tap changer (OLTC), distributed generator settings and all shunt capacitor switching on the load and DG generation profile in a day. The proposed method minimizes the real power losses and improves the voltage profile using squared deviations of bus voltages. The results indicate that the proposed method reduces the real losses and voltage fluctuations and improve receiving power factor. This paper proposes coordinated voltage and reactive power control methods that adjust optimal control values of capacitor banks, OLTC, and the AVR of DGs by using a voltage sensitivity factor (VSF) and dynamic programming (DP) with branch-and-bound (B&B) method. To avoid the computational burden, we try to limit the possible states to 24 stages by using a flexible searching space at each stage. Finally, we will show the effectiveness of the proposed method by using operational cost of real power losses and voltage deviation factor as evaluation index for a whole day in a power system with distributed generators.

• Journal of Electrical Engineering and Technology
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• v.8 no.5
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• pp.1012-1020
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• 2013

In this work, Self-adaptive Differential Evolutionary (SaDE) algorithm is proposed to solve Optimal Location and Size of Capacitor (OLSC) problem in radial distribution networks. To obtain the SaDE algorithm, two improvements have been applied on control parameters of mutation and crossover operators. To expand the study, three load conditions have been considered, i.e., constant, varying and effective loads. Objective function is introduced for the load conditions. The annual cost is fitness of problem, in addition to this cost, CPU time, voltage profile, active power loss and total installed capacitor banks and their related costs have been used for comparisons. To confirm the ability of each improvements of SaDE, the improvements are studied both in separate and simultaneous conditions. To verify the effectiveness of the proposed algorithm, it is tested on IEEE 10-bus and 34-bus radial distribution networks and compared with other approaches.

• Journal of Energy Engineering
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• v.12 no.1
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• pp.42-48
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• 2003

In system planing and operation, voltage and reactive power control is very important. The voltage deviation and system losses can be reduced through control of reactive power sources. In general, there are several different reactive power sources, we used switched shunt capacitor to improve the voltage profile and to reduce system losses. Since there are many switched shunt capacitors in power system, so it if necessary to coordinate these switched shunt capacitors. In this study, Genetic Algorithm (GA) is used to find optimal coordination of switched shunt capacitors in a local area of power system. In case study, the effectiveness of the proposed method is demonstrated in KEPCO's power system. The simulation is performed by PSS/E and the results of simulation are compared with sensitivity method.

• Journal of Electrical Engineering and Technology
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• v.7 no.1
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• pp.1-8
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• 2012

The current paper presents a novel control strategy of a three-phase, four-wire Unified Power Quality (UPQC) to improve power quality. The UPQC is realized by the integration of series and shunt active power filters (APF) sharing a common dc bus capacitor. The realization of shunt APF is carried out using a three-phase, four-leg Voltage Source Inverter (VSI), and the series APF is realized using a three-phase, three-leg VSI. To extract the fundamental source voltages as reference signals for series APF, a zero-crossing detector and sample-and-hold circuits are used. For the control of shunt APF, a simple scheme based on the real component of fundamental load current (I $Cos{\Phi}$) with reduced numbers of current sensors is applied. The performance of the applied control algorithm is evaluated in terms of power-factor correction, source neutral current mitigation, load balancing, and mitigation of voltage and current harmonics in a three-phase, four-wire distribution system for different combinations of linear and non-linear loads. The reference signals and sensed signals are used in a hysteresis controller to generate switching signals for shunt and series APFs. In this proposed UPQC control scheme, the current/voltage control is applied to the fundamental supply currents/voltages instead of fast-changing APF currents/voltages, thus reducing the computational delay and the required sensors. MATLAB/Simulink-based simulations that support the functionality of the UPQC are obtained.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.10 s.352
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• pp.90-97
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• 2006

We report our research work on the millimeter-wave broadband amplifier integrating the shunt peaking technology with the cascode configuration. The millimeter-wave broadband cascode amplifier on MIMIC technology was designed and fabricated using $0.1{\mu}m\;{\Gamma}-gate$ GaAs PHEMT, CPW, and passive library. The fabricated PHEMT has shown a transconductance of 346.3 mS/mm, a current gain cut off frequency ($f_T$) of 113 GHz, and a maximum oscillation frequency ($f_{max}$) of 180 GHz. To prevent oscillation of designed cascode amplifier, a parallel resistor and capacitor were connected to drain of common-gate device. For expansion of the bandwidth and flatness of the gain, we inserted the short stub into bias circuits and the compensation transmission line between common-source device and common-gate device, and then their lengths were optimized. Also, the input and output stages were designed using the matching method to obtain the broadband characteristic. From the measurement, we could confirm to extend bandwidth and flat gain by integrating the shunt peaking technology with the cascode configuration. The cascode amplifier shows the broadband characteristic from 19 GHz to 53.5 GHz. Also, the average gain of this amplifier is about 6.5 dB over the bandwidth.

• Journal of Energy Engineering
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• v.7 no.1
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• pp.65-72
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• 1998

This paper presents a fast calculation method for evaluating of voltage stability margin (MW) using the line flow equation in polar form. Here, Line flow equations $(P_{ij},\;Q_{ij}$ are comprised of state variable, $V_i,\;{\Delta}_i,\;V_j$ and ${Delta}_j$, and line parameter, r and x. using the feature of polar coordinate, these becomes one equation with two variables, $V_j,;V_j$. Moreover, if bus j is slack or generator bus, which is specified voltage magnitude in load flow calculation, it becomes one equation with one variable $V_ i $ that is, may be formulated with the second-order equation for $V^2_i$. Therefore, multiple load flow solutions may be obtained with simple computation. The obtained load flow multiple solutions are used for evaluating of voltage stability through sensitivity analysis or its closeness. Also, the method is proposed to calculate for voltage stability margin considering shunt capacitor, which is important element for evaluating of voltage stability. The proposed method was validated to sample systems.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.7
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• pp.784-790
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• 2012

In this paper, an all-digital CMOS ultra-wideband(UWB) pulse generator for high band(6~10 GHz) frequency range is presented. The pulse generator is designed and implemented with extremely low power and low complexity. It is designed to meet the FCC spectral mask requirement by using Gaussian pulse shaping circuit and control the center frequency by using CMOS delay line with shunt capacitor. Measurement results show that the center frequency can be controlled from 4.5 GHz to 7.5 GHz and pulse width is 1.5 ns and pulse amplitude is 310 mV peak to peak at 10 MHz pulse repetition frequency(PRF). The circuit is implemented in 0.13 um CMOS process with a core area of only $182{\times}65um^2$ and dissipates the average power of 11.4 mW at an output buffer with 1.5-V supply voltage. However, the core consumes only 0.26 mW except for output buffer.

• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.3
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• pp.274-284
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• 2003

Multi-level converter that is high-capacity electric power conversion system is used widely to electric motor drive system and FATCs(Flexible AC Transmission Systems). H-Bridge converter has been prevalently applied to shunt-type system because it can be easily expanded to the multi-level. In steady states, converter is normally operated in the range of 0.7∼0.8 of modulation Index. Even though zero vectors are not imposed to high modulation index, DC-Link voltage Is constant. It means that converter has another boost vector except for zero vectors among several vectors in 3-level converter. This paper has examined the principle of boost vector and investigated the difference between another boost vector and zero vectors in 3-level converter. In addition, this paper has analysed and compared the charging currents and the capacitor voltages of two topologies. The currents and voltages are related to reference voltage. Therefore, it proposed the calculation method for the voltage ripple and the charging current of each capacitor and compared various DC-Link voltage control methods through the simulation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.9
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• pp.1540-1548
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• 2010

KEPCO proposes enhanced voltage management system that is a coordinate voltage control system between the hierarchical voltage control system and the slow voltage control system. It has been installing in Jeju island. VMS consists of a master controller, CVC (Continuous Voltage Controller) and DVC (Discrete Voltage Controller). CVC consists of main controller, FDMU (Field Data Measurement Unit) and several RPDs (Reactive Power Dispatcher). CVC has a control scheme with AVRs of generator to maintain the voltage of a pilot bus in a power system, DVC has a control scheme with static reactive power sources, like a shunt capacitor, a shunt reactor, ULTC and so on, to maintain the reactive power reserve of a power system and a master controller is executed to recover reactive power margin of a power system through coordinated control between CVC and DVC.