• Journal of Electrical Engineering and Technology
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• v.12 no.6
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• pp.2278-2288
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• 2017

Multilevel converter topologies are widely used in many applications. The cascaded H-bridge multilevel inverter (CHBMI), which is one of many multilevel converter topologies, has been introduced as a useful topology in high and medium power. However, it has a drawback to require a lot of switches. Therefore, the reliability of CHBMI is important factor for analyzing the performance. This paper presents a simple switch fault diagnosis method for single-phase CHBMI. There are two types of switch faults: open-fault and short-fault. In the open-fault, the body diode of faulty switch provides a freewheeling current path. However, when the short-fault occurs, the distortion of output current is different from that of the open-fault because it has an unavailable freewheeling current flow path due to a disconnection of fuse. The fault diagnosis method is based on the zero current time analysis according to zero-voltage switching states. Using the proposed method, it is possible to detect the location of faulty switch accurately. The PSIM simulation and experimental results show the effectiveness of proposed switch fault diagnosis method.

• Journal of Power Electronics
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• v.9 no.6
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• pp.949-959
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• 2009

This paper presents a systematic investigation of the fault-mode behaviors of matrix converter systems. Knowledge about converter behaviors after fault occurrence is important from the standpoint of reliable system design, protection and fault-tolerant control. Converter behaviors have been, in detail, examined with both qualitative and quantitative approaches for key fault types, such as switch open-circuited faults and switch short-circuited faults. Investigating the fault-mode behaviors of matrix converters reveals that converter operation with switch short-circuited faults leads to overvoltage stresses as well as overcurrent stresses on other healthy switching components. On the other hand, switch open-circuited faults only result in overvoltage to other switching components. This study can be used to predict fault-mode converter behaviors and determine additional stresses on remaining power circuit components under fault-mode operations.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.4
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• pp.426-436
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• 1998

Identification of fault current during the operation of a power semiconductor switch and activation of suitable remedial actions are important for reliable operation of power converters. A short circuit is a basic and severe fault situation in a circuit structure such as voltage source converters. This paper presents a new active protection circuit for fast and precise clamping and safe shutdown of fault currents of the IGBTs. This circuit allows operation of the IGBTs with a higher on-state gate voltage, which can thereby reduce the conduction loss in the device without compromising the short circuit protection characteristics. The operation of the circuit is studied under various conditions, considering variation of temperature, rising rate of fault current, gate voltage value, and protection circuit parameters. An evaluation of the operation of the circuit is made using IGBTs from different to confirm the effectiveness of the protection circuit.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.5
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• pp.626-634
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• 2018

These days, widespread use of sensitive loads and distributed generators makes static transfer switch (STS) an essential component in power circuits to achieve a good power quality for AC Grids. In case of a short-circuit fault, previous STS cannot break the fault current. However, the proposed STS has the capability of breaking it quickly as a circuit breaker. Also if there are power quality problems such as Sag/Swell, the proposed STS can quickly transfers the load to the good quality source. Furthermore it is proved that the transfer time of the proposed STS is within one half of period of 3-phase source frequency regardless of the type of load. It is anticipated that the proposed STS may be utilized to realize many stable and reliable AC grid systems.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.116-126
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• 1994

In this paper, the switch-level fault simulator for CMOS circuits with a gate-to-drain/source short fault is implemented. A fault model used in this paper is based on the graphical analysis of the electrical characteristics of the faulty MOS devices and the conversion of the faulty CMOS circuit to the equivalent faulty CMOS inverter in order to find its effect on the successive stage. This technique is very simple and has the increased accuracy of the simulation. The simulation result of the faulty circuit using the implemented fault simulator is compared with the result of the SPICE simulation.

• Journal of Power Electronics
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• v.10 no.6
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• pp.702-708
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• 2010

In this paper, a fault diagnosis algorithm for brushless DC (BLDC) motor drives is proposed to maintain control performance under switch open-damage. The proposed fault diagnosis algorithm consists of a simple algorithm using measured phase current information and it detects open-circuit faults based on the operating characteristic of BLDC motors. The proposed algorithm quickly recovers control performance due to its short detection time and its reconfiguration of the system topology. It can be embedded into existing BLDC drive software as a subroutine without additional sensors. The feasibility of the proposed fault diagnosis algorithm is proven by simulation and experimental results.

• Proceedings of the KIEE Conference
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• 2007.11b
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• pp.154-155
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• 2007

Increase of fault current due to larger power demand has increased the possibility of the breakdown of the power system. To protect the power system effectively from the larger fault current, several countermeasures have been proposed. Among them, the superconducting fault current limiter (SFCL) has been expected as one of the most effective solutions. In this paper, the fault current limiter, which consists of a ideal switch as a trigger part and the limiter as the limiting part, has been applied into the distribution system. From the analysis for the fault current limiting operation of SFCL, the inserting resistance's magnitude has been confirmed to affect OCR trip time in a short-circuit of distribution system.

• Progress in Superconductivity and Cryogenics
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• v.13 no.1
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• pp.41-45
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• 2011

Hybrid fault current limiters (FCL) have been researched at Yonsei University. The hybrid FCL has advantages such as having a rapid response to a sudden fault situation and a fast recovery time from a quench. It consists of an asymmetric HTS coil, a switching module, and a bypass reactor. The asymmetric HTS coil is wound with two different types of HTS wires in an opposite direction so that it has nearly zero inductance at the superconducting state. When the quench occurs at the fault state, a strong magnetic field is generated from the asymmetric coil because of different quench characteristics of two HTS wires, and then a repulsive force is induced in the switching module. The force opens the switch and the fault current is pushed into the bypass reactor. In this research, we analyzed the cause of the repulsive force and confirmed, experimentally and computationally, that the magnitude of a repulsive force is varied by changing the gap distance between the asymmetric coil and the switching module. By using the FEM simulation, we calculated the repulsive force with respect to the gap distance and verified that the effect of the gap distance. Then, short circuit test was carried out to confirm the correct operation of the fast switch.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1298-1305
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• 2016

This paper presents the development of a short-circuit protection mechanism on a high voltage switch (HVS) board which is built by a series connection of semiconductor switches. The HVS board is able to quickly detect and limit the peak fault current before the signal board triggers off a gate signal. Voltage clamping techniques are used to safely turn off the short-circuit current and to prevent overvoltage of the series-connected switches. The selection method of the main devices and the development of the HVS board are described in detail. Experimental results have demonstrated that the HVS board is capable of withstanding a short-circuit current at a rated voltage of 10kV without a di/dt slowing down inductor. The corresponding short-circuit current is restricted to 125 A within 100 ns and can safely turn off within 120 ns.

• Progress in Superconductivity and Cryogenics
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• v.7 no.4
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• pp.28-31
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• 2005

To verify the feasibility of bifilar winding type superconducting fault current limiter (SFCL) using BSCCO tape, two types of magnets were fabricated and tested by short-circuit in this research. Even if the FCL using high Tc superconducting (HTS) tape has zero resistance in normal state, it needs to be wound as a bifilar winding for zero inductance. Solenoid type and pancake type bifilar winding magnets are designed and fabricated with the same length of BSCCO tape. The test system consists of AC power supply, transformer, fault switch, load and bifilar winding magnet. The applied AC voltages during fault duration, 0.1s, were from 0.5V to 20V. The test results without bifilar winding magnet were compared with those with each type magnets. The test results include voltage against magnet, transport current and generated resistance curve. Thermal stability, the recovery time, was studied from the results of two type magnets. The pancake type was the most effective to limit fault current but the solenoid type was thermally the most stable. From this research, short-circuit characteristics of the two types were obtained.